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    Phase-Changeable Random Access Memory Devices Including Barrier Layers and Metal Silicide Layers
    1.
    发明申请
    Phase-Changeable Random Access Memory Devices Including Barrier Layers and Metal Silicide Layers 审中-公开
    包括阻挡层和金属硅化物层的相变型随机存取存储器件

    公开(公告)号：US20100181549A1

    公开(公告)日：2010-07-22

    申请号：US12687276

    申请日：2010-01-14

    申请人： Song-Yi Kim ,  Heung-Jin Joo ,  Dae-Hwan Kang ,  Ji-Hyun Jeong ,  Jun-Hyok Kong

    发明人： Song-Yi Kim ,  Heung-Jin Joo ,  Dae-Hwan Kang ,  Ji-Hyun Jeong ,  Jun-Hyok Kong

    IPC分类号： H01L47/00

    CPC分类号： H01L45/1625 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144

    摘要： A PRAM device may include an insulating interlayer, a diode, a metal silicide layer, a barrier spacer, an outer spacer, a lower electrode, a phase-changeable layer and an upper electrode. The insulating interlayer may be formed on a substrate. The insulating interlayer may have a contact hole. The diode may be formed in the contact hole. The metal silicide layer may be formed on the diode. The barrier spacer may be formed on an upper surface of the metal silicide layer and a side surface of the contact hole. The outer spacer may be formed on the barrier spacer. The lower electrode may be formed on the barrier spacer. The phase-changeable layer may be formed on the lower electrode. The upper electrode may be formed on the phase-changeable layer.

    摘要翻译： PRAM器件可以包括绝缘中间层，二极管，金属硅化物层，隔离隔离物，外隔离物，下电极，相变层和上电极。 绝缘中间层可以形成在基板上。 绝缘中间层可以具有接触孔。 二极管可以形成在接触孔中。 金属硅化物层可以形成在二极管上。 隔离间隔物可以形成在金属硅化物层的上表面和接触孔的侧表面上。 外隔离物可以形成在隔离隔离物上。 下电极可以形成在阻挡间隔物上。 相变层可以形成在下电极上。 上电极可以形成在相变层上。

    Multiple stacked capacitors formed within an opening with thick capacitor dielectric
    2.
    发明授权
    Multiple stacked capacitors formed within an opening with thick capacitor dielectric 失效
    形成在具有厚电容电介质的开口内的多个堆叠电容器

    公开(公告)号：US07105418B2

    公开(公告)日：2006-09-12

    申请号：US10997408

    申请日：2004-11-24

    申请人： Heung-Jin Joo

    发明人： Heung-Jin Joo

    IPC分类号： H01L21/20

    CPC分类号： H01L28/91 ,  H01L27/0207 ,  H01L27/10852 ,  H01L28/55

    摘要： For forming stacked capacitors, an opening is formed through at least one semiconductor material. A lower electrode material is patterned within the opening to form a plurality of lower electrodes within the opening. The stacked capacitors are formed with the lower electrodes within the opening by depositing a capacitor dielectric and an upper electrode within the opening. With such a relatively large opening, a capacitor dielectric of the stacked capacitors is deposited with a large thickness for improving reliability of the stacked capacitors.

    摘要翻译： 为了形成叠层电容器，通过至少一种半导体材料形成开口。 在开口内图案化下电极材料，以在开口内形成多个下电极。 堆叠的电容器通过在开口内沉积电容器电介质和上电极而在开口内由下电极形成。 通过这样一个比较大的开口，叠层电容器的电容器电介质被沉积成较大的厚度，以提高叠层电容器的可靠性。

    Node structures under capacitor in ferroelectric random access memory device and methods of forming the same
    4.
    发明申请
    Node structures under capacitor in ferroelectric random access memory device and methods of forming the same 审中-公开
    铁电随机存取存储器件中电容器下的节点结构及其形成方法

    公开(公告)号：US20080111171A1

    公开(公告)日：2008-05-15

    申请号：US11811931

    申请日：2007-06-12

    申请人： Heung-Jin Joo ,  Yoon-Jong Song ,  Ki-Nam Kim

    发明人： Heung-Jin Joo ,  Yoon-Jong Song ,  Ki-Nam Kim

    IPC分类号： H01L29/94 ,  H01L21/02

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55

    摘要： In a node structure under a capacitor in a ferroelectric random access memory device and a method of forming the same, top surfaces of the node structures are disposed at substantially the same level as a top surface of an interlayer insulating layer surrounding the node structures, and thus crystal growth of a ferroelectric in the capacitor can be stabilized. To this end, a node insulating pattern is formed on a semiconductor substrate. A node defining pattern surrounding the node insulating pattern is disposed under the node insulating pattern. A node conductive pattern is disposed between the node defining pattern and the node insulating pattern.

    摘要翻译： 在铁电随机存取存储器件中的电容器下的节点结构及其形成方法中，节点结构的顶表面设置在与节点结构周围的层间绝缘层的顶表面基本相同的水平处，并且 因此可以使电容器中的铁电体的晶体生长稳定。 为此，在半导体衬底上形成节点绝缘图案。 定义节点绝缘图案周围的节点的节点设置在节点绝缘图案之下。 节点导电图案设置在节点限定图案和节点绝缘图案之间。

    Semiconductor memory device and method for forming the same
    5.
    发明申请
    Semiconductor memory device and method for forming the same 审中-公开
    半导体存储器件及其形成方法

    公开(公告)号：US20080061334A1

    公开(公告)日：2008-03-13

    申请号：US11896952

    申请日：2007-09-07

    申请人： Ju-Young Jung ,  Suk-Ho Joo ,  Jung-Hoon Park ,  Heung-Jin Joo ,  Hee-San Kim ,  Seung-Kuk Kang ,  Do-Yeon Choi

    发明人： Ju-Young Jung ,  Suk-Ho Joo ,  Jung-Hoon Park ,  Heung-Jin Joo ,  Hee-San Kim ,  Seung-Kuk Kang ,  Do-Yeon Choi

    IPC分类号： H01L29/94 ,  H01L21/02

    CPC分类号： H01L27/11507 ,  H01L21/76849 ,  H01L21/7687 ,  H01L23/5226 ,  H01L27/11502 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor memory device and a method for forming the same. The method includes forming an insulating layer on a semiconductor substrate having a conductive region, forming a contact hole that exposes the conductive region by etching the insulating layer, forming a barrier metal layer that covers a sidewall and a bottom of the contact hole, and forming a contact plug in the contact hole by interposing the barrier metal layer therebetween. An etching process may be preformed that recesses the barrier metal layer and the contact plug in such a manner that a top surface of the contact plug protrudes upward beyond a top surface of the barrier metal layer. A capping plug may be formed covering the recessed barrier metal layer and the recessed contact plug. A capacitor may be formed on the capping plug.

    摘要翻译： 一种半导体存储器件及其形成方法。 该方法包括在具有导电区域的半导体衬底上形成绝缘层，形成通过蚀刻绝缘层而暴露导电区域的接触孔，形成覆盖接触孔的侧壁和底部的阻挡金属层，以及形成 通过在其间插入阻挡金属层，在接触孔中形成接触塞。 可以进行蚀刻工艺，其以使得接触插头的顶表面向上突出超过阻挡金属层的顶表面的方式使阻挡金属层和接触插塞凹陷。 可以形成覆盖凹陷的阻挡金属层和凹入的接触插塞的封盖塞。 可以在封盖上形成电容器。

    Multiple stacked capacitors formed within an opening with thick capacitor dielectric
    7.
    发明授权
    Multiple stacked capacitors formed within an opening with thick capacitor dielectric 失效
    形成在具有厚电容电介质的开口内的多个堆叠电容器

    公开(公告)号：US07262453B2

    公开(公告)日：2007-08-28

    申请号：US11496384

    申请日：2006-07-31

    申请人： Heung-Jin Joo

    发明人： Heung-Jin Joo

    IPC分类号： H01L21/336

    CPC分类号： H01L28/91 ,  H01L27/0207 ,  H01L27/10852 ,  H01L28/55

    摘要： For forming stacked capacitors, an opening is formed through at least one semiconductor material. A lower electrode material is patterned within the opening to form a plurality of lower electrodes within the opening. The stacked capacitors are formed with the lower electrodes within the opening by depositing a capacitor dielectric and an upper electrode within the opening. With such a relatively large opening, a capacitor dielectric of the stacked capacitors is deposited with a large thickness for improving reliability of the stacked capacitors.

    摘要翻译： 为了形成叠层电容器，通过至少一种半导体材料形成开口。 在开口内图案化下电极材料，以在开口内形成多个下电极。 堆叠的电容器通过在开口内沉积电容器电介质和上电极而在开口内由下电极形成。 通过这样一个比较大的开口，叠层电容器的电容器电介质被沉积成较大的厚度，以提高叠层电容器的可靠性。

    Multiple stacked capacitors formed within an opening with thick capacitor dielectric
    9.
    发明申请
    Multiple stacked capacitors formed within an opening with thick capacitor dielectric 失效

    公开(公告)号：US20060261396A1

    公开(公告)日：2006-11-23

    申请号：US11496384

    申请日：2006-07-31

    申请人： Heung-Jin Joo

    发明人： Heung-Jin Joo

    IPC分类号： H01L29/94

    CPC分类号： H01L28/91 ,  H01L27/0207 ,  H01L27/10852 ,  H01L28/55

    摘要： For forming stacked capacitors, an opening is formed through at least one semiconductor material. A lower electrode material is patterned within the opening to form a plurality of lower electrodes within the opening. The stacked capacitors are formed with the lower electrodes within the opening by depositing a capacitor dielectric and an upper electrode within the opening. With such a relatively large opening, a capacitor dielectric of the stacked capacitors is deposited with a large thickness for improving reliability of the stacked capacitors.

    Methods for forming electronic devices including capacitor structures
    10.
    发明授权
    Methods for forming electronic devices including capacitor structures 失效
    用于形成包括电容器结构的电子器件的方法

    公开(公告)号：US06911362B2

    公开(公告)日：2005-06-28

    申请号：US10635195

    申请日：2003-08-06

    申请人： Ki-Nam Kim ,  Yoon-Jong Song ,  Heung-Jin Joo

    发明人： Ki-Nam Kim ,  Yoon-Jong Song ,  Heung-Jin Joo

    IPC分类号： H01L27/105 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/8242

    CPC分类号： H01L27/11502 ,  H01L27/11507

    摘要： Methods for forming an electronic device can include forming a capacitor structure on a portion of a substrate with the capacitor structure including a first electrode on the substrate, a capacitor dielectric on the first electrode, a second electrode on the dielectric, and a hard mask on the second electrode. More particularly, the capacitor dielectric can be between the first and second electrodes, the first electrode and the capacitor dielectric can be between the second electrode and the substrate, and the first and second electrodes and the capacitor dielectric can be between the hard mask and the substrate. An interlayer dielectric layer can be formed on the hard mask and on portions of the substrate surrounding the capacitor structure, and portions of the interlayer dielectric layer can be removed to expose the hard mask while maintaining portions of the interlayer dielectric layer on portions of the substrate surrounding the capacitor structure. The hard mask can then be removed thereby exposing portions of the second electrode while maintaining the portions of the interlayer dielectric layer on portions of the substrate surrounding the capacitor.

    摘要翻译： 用于形成电子器件的方法可以包括在衬底的一部分上形成电容器结构，其中电容器结构包括在衬底上的第一电极，第一电极上的电容器电介质，电介质上的第二电极， 第二电极。 更具体地，电容器电介质可以在第一和第二电极之间，第一电极和电容器电介质可以在第二电极和衬底之间，并且第一和第二电极和电容器电介质可以在硬掩模和第二电极之间 基质。 可以在硬掩模和围绕电容器结构的基板的部分上形成层间电介质层，并且可以去除层间介电层的部分以暴露硬掩模，同时将层间电介质层的部分保持在基板的部分上 围绕电容器结构。 然后可以去除硬掩模，从而暴露第二电极的部分，同时保持层间电介质层的部分在包围电容器的基板的部分上。