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    Semiconductor recessed mask interconnect technology
    2.
    发明授权
    Semiconductor recessed mask interconnect technology 失效
    半导体凹陷掩模互连技术

    公开(公告)号：US06657305B1

    公开(公告)日：2003-12-02

    申请号：US09703734

    申请日：2000-11-01

    申请人： Stephen Alan Cohen ,  Timothy Joseph Dalton ,  John Anthony Fitzsimmons ,  Stephen McConnell Gates ,  Brian Wayne Herbst ,  Sampath Purushothaman ,  Stanley Joseph Whitehair

    发明人： Stephen Alan Cohen ,  Timothy Joseph Dalton ,  John Anthony Fitzsimmons ,  Stephen McConnell Gates ,  Brian Wayne Herbst ,  Sampath Purushothaman ,  Stanley Joseph Whitehair

    IPC分类号： H01L2348

    CPC分类号： H01L21/76829 ,  H01L21/76804 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal plus low dielectric constant (low-k) interconnect structure is provided for a semiconductor device wherein adjacent regions in a surface separated by a dielectric have dimensions in width and spacing in the sub 250 nanometer range, and in which reduced lateral leakage current between adjacent metal lines, and a lower effective dielectric constant than a conventional structure, is achieved by the positioning of a differentiating or mask member that is applied for the protection of the dielectric in subsequent processing operations, at a position about 2-5 nanometers below a, to be planarized, surface where there will be a lower electric field. The invention is particularly useful in the damascene type device structure in the art wherein adjacent conductors extend from a substrate through an interlevel dielectric material, connections are made in a trench, a diffusion barrier liner is provided in the interlevel dielectric material and masking is employed to protect the dielectric material between conductors during processing operations.

    摘要翻译： 为半导体器件提供金属加上低介电常数（低k）互连结构，其中由电介质隔开的表面中的相邻区域在亚250纳米范围内具有宽度和间距的尺寸，并且其中减小横向漏电流 相邻的金属线和比常规结构更低的有效介电常数是通过在后续处理操作中在约2-5纳米以下的位置处定位用于保护电介质的微分或掩模构件来实现的 ，要平坦化，会有较低电场的表面。 本发明特别适用于本领域的镶嵌型器件结构，其中相邻导体从衬底延伸通过层间电介质材料，在沟槽中形成连接，在层间电介质材料中提供扩散阻挡衬垫，并且使用掩模 在处理操作期间保护导体之间的电介质材料。

    Spin-on cap layer, and semiconductor device containing same
    3.
    发明授权
    Spin-on cap layer, and semiconductor device containing same 有权
    旋转盖层，以及包含其的半导体器件

    公开(公告)号：US06724069B2

    公开(公告)日：2004-04-20

    申请号：US09827160

    申请日：2001-04-05

    申请人： Timothy Joseph Dalton ,  Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Christy Sensenich Tyberg

    发明人： Timothy Joseph Dalton ,  Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Christy Sensenich Tyberg

    IPC分类号： H01L2358

    CPC分类号： H01L21/76835 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A spin-on cap useful as a post-CMP cap for Cu interconnect structures is provided. The inventive spin-on cap includes a low-k dielectric (on the order of 3.5 or less) and at least one additive. The at least one additive employed in the present invention is capable of binding Cu ions, and is soluble in the spun-on low-k dielectric. The spin-on cap of the present invention may further include a spun-on low-k (on the order of 3.5 or less) reactive-ion etch (RIE) stop layer. Spin-on caps containing a bilayer of low-dielectric plus at least additive and low-k RIE stop layer are preferred. It is noted that the inventive spin-on cap of the present invention does not significantly increase the effective dielectric constant of the interconnect structure and does not add additional cost to the fabrication of the interconnect structure since a single deposition tool, i.e., spin coating tool, is employed. Moreover, because of the presence of the additive in the spin-on cap, Cu migration is substantially minimized.

    摘要翻译： 提供了一种用作Cu互连结构的CMP后盖的旋涂帽。 本发明的旋涂帽包括低k电介质（约3.5或更小）和至少一种添加剂。 本发明中使用的至少一种添加剂能够结合Cu离子，并且可溶于旋转的低k电介质。 本发明的旋涂帽还可以包括旋转低k（约3.5或更小）反应离子蚀刻（RIE）停止层。 包含低电介质加上至少添加和低k RIE停止层的双层的旋转盖是优选的。 注意，本发明的本发明的旋涂帽不会显着增加互连结构的有效介电常数，并且不会增加互连结构的制造的额外成本，因为单个沉积工具，即旋涂工具 ，被雇用。 此外，由于在旋涂帽中存在添加剂，所以Cu迁移基本上被最小化。

    Cu/low-k BEOL with nonconcurrent hybrid dielectric interface
    4.
    发明授权
    Cu/low-k BEOL with nonconcurrent hybrid dielectric interface 有权
    具有非并联混合电介质界面的Cu / low-k BEOL

    公开(公告)号：US06548901B1

    公开(公告)日：2003-04-15

    申请号：US09596750

    申请日：2000-06-15

    申请人： William Cote ,  Timothy Joseph Dalton ,  Daniel Charles Edelstein ,  Stephen McConnell Gates

    发明人： William Cote ,  Timothy Joseph Dalton ,  Daniel Charles Edelstein ,  Stephen McConnell Gates

    IPC分类号： H01L2348

    CPC分类号： H01L23/5222 ,  H01L21/768 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure having reduced fringing fields of bottom corners of said interconnect structure and a method of fabricating the same is provided. The interconnect structure includes one or more interconnect levels one on top of each other, wherein each interconnect level is separated by a diffusion barrier and includes a dielectric stack of at least one low-k interlayer dielectric on at least one hybrid dielectric, said dielectrics having planar interfaces therebetween, each interconnect level further comprising metallic lines formed in said low-k interlayer dielectric, with the proviso that bottom horizontal portions of said metallic lines are not coincident with said interface, and said metallic lines are contained within said low-k interlayer dielectric. The interconnect structures may be fabricated such that top horizontal portions of the metallic lines are coplanar with a top surface of the low-k interlayer dielectric.

    摘要翻译： 提供具有减小所述互连结构的底角的边缘的互连结构及其制造方法。 互连结构包括彼此之上的一个或多个互连层，其中每个互连层由扩散阻挡隔开，并且包括在至少一个混合电介质上的至少一个低k​​层间电介质的电介质叠层，所述电介质具有 每个互连层还包括形成在所述低k层间电介质中的金属线，条件是所述金属线的底部水平部分与所述界面不一致，并且所述金属线包含在所述低k层间电介质中 电介质。 可以制造互连结构，使得金属线的顶部水平部分与低k层间电介质的顶表面共面。