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    Methods to improve copper-fluorinated silica glass interconnects
    3.
    发明授权
    Methods to improve copper-fluorinated silica glass interconnects 有权
    改善铜氟化石英玻璃互连的方法

    公开(公告)号：US6136680A

    公开(公告)日：2000-10-24

    申请号：US489498

    申请日：2000-01-21

    申请人： Jane-Bai Lai ,  Chung-Shi Liu ,  Tien-I Bao ,  Syun-Ming Jang ,  Chung-Long Chang ,  Hui-Ling Wang ,  Szu-An Wu ,  Wen-Kung Cheng ,  Chun-Ching Tsan ,  Ying-Lang Wang

    发明人： Jane-Bai Lai ,  Chung-Shi Liu ,  Tien-I Bao ,  Syun-Ming Jang ,  Chung-Long Chang ,  Hui-Ling Wang ,  Szu-An Wu ,  Wen-Kung Cheng ,  Chun-Ching Tsan ,  Ying-Lang Wang

    IPC分类号： H01L21/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/76825 ,  H01L21/02074 ,  H01L21/3105 ,  H01L21/3212 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76883

    摘要： A method of forming an interconnect, comprising the following steps. A semiconductor structure is provided that has an exposed first metal contact and a dielectric layer formed thereover. An FSG layer having a predetermined thickness is then formed over the dielectric layer. A trench, having a predetermined width, is formed within the FSG layer and the dielectric layer exposing the first metal contact. A barrier layer, having a predetermined thickness, may be formed over the FSG layer and lining the trench side walls and bottom. A metal, preferably copper, is then deposited on the barrier layer to form a copper layer, having a predetermined thickness, over said barrier layer covered FSG layer, filling the lined trench and blanket filling the barrier layer covered FSG layer. The copper layer, and the barrier layer on said upper surface of said FSG layer, are planarized, exposing the upper surface of the FSG layer and forming a planarized copper filled trench. The FSG layer and planarized copper filled trench are then processed by either: (1) annealing from about 400 to 450.degree. C. for about one hour, then either NH.sub.3 or H.sub.2 plasma treating; or (2) Ar.sup.+ sputtering to ion implant Ar.sup.+ to a depth of less than about 300 .ANG. in the fluorinated silica glass layer, whereby any formed Si--OH bonds and copper oxide (metal oxide) are removed. A dielectric cap layer, having a predetermined thickness, is then formed over the processed FSG layer and the planarized copper filled trench.

    摘要翻译： 一种形成互连的方法，包括以下步骤。 提供一种半导体结构，其具有暴露的第一金属触点和形成在其上的电介质层。 然后在电介质层上形成具有预定厚度的FSG层。 具有预定宽度的沟槽形成在FSG层内，并且介电层露出第一金属接触。 具有预定厚度的阻挡层可以形成在FSG层之上并且衬在沟槽侧壁和底部。 然后将一种金属，优选铜沉积在阻挡层上，以形成具有预定厚度的铜层，超过所述阻挡层覆盖的FSG层，填充衬里的沟槽和覆盖填充阻挡层覆盖的FSG层的毯子。 所述FSG层的所述上表面上的铜层和阻挡层被平坦化，暴露出FSG层的上表面并形成平坦化的铜填充沟槽。 然后通过以下步骤之一处理FSG层和平坦化的铜填充沟槽：（1）从约400至450℃的退火约1小时，然后进行NH 3或H 2等离子体处理; 或者（2）在氟化石英玻璃层中，离子注入Ar +溅射至小于约300的深度，由此除去任何形成的Si-OH键和氧化铜（金属氧化物）。 然后在经处理的FSG层和平坦化的铜填充沟槽上形成具有预定厚度的电介质盖层。

    Method of reducing phase transition temperature by using silicon-germanium alloys
    4.
    发明授权
    Method of reducing phase transition temperature by using silicon-germanium alloys 有权
    使用硅锗合金降低相变温度的方法

    公开(公告)号：US06399487B1

    公开(公告)日：2002-06-04

    申请号：US09222269

    申请日：1998-12-28

    申请人： Jane-Bai Lai ,  Lih-Juan Chen ,  Chung-Shi Liu ,  Chen-Hua Yu

    发明人： Jane-Bai Lai ,  Lih-Juan Chen ,  Chung-Shi Liu ,  Chen-Hua Yu

    IPC分类号： H01L2144

    CPC分类号： H01L29/41783 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

    摘要： An improved SALICIDE process is described wherein the transformation temperature to a lower resistivity suicide structure is reduced by first coating with a layer of a silicon-germanium alloy prior to the deposition of the titanium layer. Provided there is at least 40 atomic percent of germanium in the alloy a second RTA at a temperature no higher than about 650° C. may be effectively used. The resulting ternary alloy has a resistivity of about 15-20 microhm cm which corresponds to a sheet resistance of about 3-3.5 ohms per square. The ability to achieve low sheet resistance after annealing at such a low temperature becomes increasingly more important as device dimensions decrease since the second RTA becomes increasingly more likely to result in agglomeration of the silicidelayer.

    摘要翻译： 描述了改进的SALICIDE方法，其中通过在沉积钛层之前首先用一层硅 - 锗合金涂层来降低到较低电阻率硅化物结构的转变温度。 如果在合金中存在至少40原子％的锗，则可以有效地使用不高于约650℃的温度的第二RTA。 得到的三元合金具有约15-20微米厘米的电阻率，其对应于约3-3.5欧姆/平方的薄层电阻。 在这样低的温度下退火之后实现低的薄层电阻的能力变得越来越重要，因为器件尺寸减小，因为第二RTA变得越来越多地导致硅化物层的聚集。

    Damascene method employing composite etch stop layer
    5.
    发明授权
    Damascene method employing composite etch stop layer 有权
    使用复合蚀刻停止层的镶嵌方法

    公开(公告)号：US07187084B2

    公开(公告)日：2007-03-06

    申请号：US10760905

    申请日：2004-01-20

    申请人： Syun-Ming Jang ,  Chung-Shi Liu ,  Chen-Hua Yu

    发明人： Syun-Ming Jang ,  Chung-Shi Liu ,  Chen-Hua Yu

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L21/76832 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/31127 ,  H01L21/31138 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/76807

    摘要： A damascene structure is provided comprising a substrate, a lower intermetal dielectric layer over the substrate, an exposed conductive structure within the lower intermetal dielectric layer, a composite etch stop layer over the lower intermetal dielectric layer and the exposed conductive structure; the composite etch stop layer comprising a first lower sub-layer and a second upper sub-layer, an upper intermetal dielectric layer over the composite etch stop layer, a trench interconnection opening forming within the upper intermetal dielectric layer and the composite etch stop layer, the trench interconnection opening exposing the conductive structure, a barrier metal layer at least lining the trench interconnection opening. and a conductor plug within the trench interconnection opening, contacting the conductive structure. The upper surface of the barrier metal layer is coplanar with the upper surface of the conductor plug.

    摘要翻译： 提供一种镶嵌结构，其包括基底，在该基底上的下部金属间电介质层，该下部金属间电介质层内的暴露的导电结构，该下部金属间介电层上的复合蚀刻停止层和该暴露的导电结构; 所述复合蚀刻停止层包括第一下部子层和第二上部子层，复合蚀刻停止层上方的上部金属间介电层，在上部金属间介电层和复合蚀刻停止层中形成的沟槽互连开口， 所述沟槽互连开口暴露所述导电结构，至少衬垫所述沟槽互连开口的阻挡金属层。 以及沟槽互连开口内的导体插头，与导电结构接触。 阻挡金属层的上表面与导体插塞的上表面共面。

    Passivation method of post copper dry etching
    6.
    发明授权
    Passivation method of post copper dry etching 有权
    后铜干蚀刻钝化法

    公开(公告)号：US06277745B1

    公开(公告)日：2001-08-21

    申请号：US09221965

    申请日：1998-12-28

    申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Syun-Ming Jang ,  Chen-Hua Yu

    发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Syun-Ming Jang ,  Chen-Hua Yu

    IPC分类号： H01L2144

    CPC分类号： H01L21/02071 ,  H01L21/321 ,  H01L21/32136 ,  H01L21/76841 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76885

    摘要： The present invention relates to a new structure and method for the passivation of copper electrical interconnects for the semiconductor industry. More particularly, the invention details a convenient method for completing the passivation of copper lines after they have been patterned by a dry etch process. The method includes the formation of a sandwich structure consisting of a bottom barrier layer, a copper layer and a top barrier layer. After the sandwich structure is patterned with a dry etch, for example, the resultant exposed copper sidewalls are then passivated by means of a barrier metal spacer process. The fully encapsulated copper lines are highly resistant to oxidation, which is an, otherwise, inherent problem associated with the lack of self passivation/exhibited by bare copper films.

    摘要翻译： 本发明涉及用于半导体工业的铜电互连钝化的新结构和方法。 更具体地，本发明详细描述了在通过干蚀刻工艺对其进行图案化之后完成铜线钝化的方便方法。 该方法包括形成由底部阻挡层，铜层和顶部阻挡层组成的夹层结构。 在用干蚀刻图案化夹层结构之后，然后通过阻挡金属间隔物工艺钝化所得到的暴露的铜侧壁。 完全封装的铜线具有很高的抗氧化性，这是另一种与裸铜膜缺乏自钝化/显示相关的固有问题。

    Damascene method employing composite etch stop layer
    7.
    发明授权
    Damascene method employing composite etch stop layer 失效
    使用复合蚀刻停止层的镶嵌方法

    公开(公告)号：US06734110B1

    公开(公告)日：2004-05-11

    申请号：US09418031

    申请日：1999-10-14

    申请人： Syun-Ming Jang ,  Chung-Shi Liu ,  Chen-Hua Yu

    发明人： Syun-Ming Jang ,  Chung-Shi Liu ,  Chen-Hua Yu

    IPC分类号： H01L21302

    CPC分类号： H01L21/76832 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/31127 ,  H01L21/31138 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/76807

    摘要： A method for forming within a substrate employed within a microelectronics fabrication a damascene multi-layer conductor interconnection layer with inhibited/attenuated damage to a conductor stud layer accessed therein within a trench, when forming the trench interconnection pattern within a dielectric layer overlying the conductor stud layer. There is provided a substrate having a contact region formed therein employing a first intermediate metal dielectric (IMD) layer having a pattern of via contact holes etched through the IMD layer filled with studs of conductor material. There is then planarized the surface of the IMD contact region. There is then formed over the planarized first IMD layer contact region a blanket composite etch stop layer. There is the formed over the blanket composite etch stop layer a second blanket inter-level metal dielectric (IMD) layer. A patterned photoresist etch mask layer formed into the interconnection trench pattern is then formed over the substrate and employed to transfer the trench pattern into the second IMD layer and the upper sub-layer of the composite etch stop layer. The interconnection trench pattern is then transferred by a second subtractive etch into the lower sub-layer of the composite etch stop layer, employing the second IMD layer as an etch mask. A barrier metal layer is then formed over the substrate. The trench pattern is then filled with a second conductor material to complete the damascene multi-layer conductor interconnection layer, with improved electrical conductivity and contact properties and inhibited/attenuated degradation effects due to processing on the damascene interconnection layer.

    摘要翻译： 一种用于在微电子学制造中使用的衬底内形成的镶嵌多层导体互连层的方法，其在沟槽内存在于其中的导体柱层的受损/衰减损伤时，当在覆盖导体柱的电介质层内形成沟槽互连图案时 层。 提供了一种其中形成有接触区域的基板，其中采用第一中间金属电介质（IMD）层，其具有通过填充有导体材料柱的IMD层蚀刻的通孔接触孔的图案。 然后平面化IMD接触区域的表面。 然后在平坦化的第一IMD层接触区域上形成覆盖复合蚀刻停止层。 在覆盖层复合蚀刻停止层上形成第二毯层级金属电介质（IMD）层。 形成在互连沟槽图案中的图案化的光致抗蚀剂蚀刻掩模层然后形成在衬底上并用于将沟槽图案转移到复合蚀刻停止层的第二IMD层和上部子层中。 然后通过第二减法蚀刻将互连沟槽图案转移到复合蚀刻停止层的下部子层中，采用第二IMD层作为蚀刻掩模。 然后在衬底上形成阻挡金属层。 然后用第二导体材料填充沟槽图案以完成镶嵌多层导体互连层，具有改善的导电性和接触性能以及由于在镶嵌互连层上的加工而被抑制/减弱的降解效应。

    Method for selective growth of Cu3Ge or Cu5Si for passivation of damascene copper structures and device manufactured thereby
    8.
    发明授权
    Method for selective growth of Cu3Ge or Cu5Si for passivation of damascene copper structures and device manufactured thereby 有权
    选择性生长Cu3Ge或Cu5Si用于钝化镶嵌铜结构的方法及其制造的器件

    公开(公告)号：US06181013B2

    公开(公告)日：2001-01-30

    申请号：US09524521

    申请日：2000-03-13

    申请人： Chung-Shi Liu ,  Chen-Hua Yu ,  Tien-I Bao ,  Syun-Ming Jang

    发明人： Chung-Shi Liu ,  Chen-Hua Yu ,  Tien-I Bao ,  Syun-Ming Jang

    IPC分类号： H01L2348

    CPC分类号： H01L21/76867 ,  H01L21/7684 ,  H01L21/76849

    摘要： Form a dielectric layer on a surface of a conductive substrate with a trench through the top surface down to the substrate. Form a barrier layer over the dielectric layer including the exposed surface of the conductive substrate and the exposed sidewalls of the dielectric layer. Form a copper conductor over the barrier layer and overfilling the narrow hole in the trench. Etch away material from the surface of the copper conductor by a CMP process lowering the copper leaving a thin layer of copper over the barrier layer above the dielectric layer aside from the hole. Form a copper passivation by combining an element selected from silicon and germanium with copper on the exposed surfaces of the copper surfaces forming an interface in the narrower hole between the copper and the copper compound located below the dielectric top level. Etch away material from the surface of the copper compound and the barrier layer to planarize the copper compound by etching down to the dielectric top level leaving a thin layer of the copper passivation compound covering the copper conductor in the narrower hole.

    摘要翻译： 在具有沟槽的导电基底的表面上形成电介质层，通过顶表面向下延伸到衬底。 在包括导电基板的暴露表面和电介质层的暴露的侧壁的电介质层上形成阻挡层。 在阻挡层上形成一个铜导体，并且填充沟槽中的窄孔。 通过CMP工艺从铜表面蚀刻掉材料，在除了孔之外的电介质层之上的阻挡层上方，降低铜，从而留下薄的铜层。 通过将选自硅和锗的元素与铜的暴露表面上的铜组合形成铜钝化，在铜和化合物之间的较窄的孔中形成界面，位于电介质顶层之下。 从铜化合物的表面和阻挡层的表面蚀刻掉材料以通过蚀刻到电介质顶部水平来平坦化铜化合物，留下覆盖较窄孔中的铜导体的铜钝化化合物的薄层。

    Method for selective growth of Cu.sub.3 Ge or Cu.sub.5 Si for passivation of damascene copper structures and device manufactured thereby
    9.
    发明授权
    Method for selective growth of Cu.sub.3 Ge or Cu.sub.5 Si for passivation of damascene copper structures and device manufactured thereby 有权
    选择性生长Cu3Ge或Cu5Si用于钝化镶嵌铜结构的方法及其制造的器件

    公开(公告)号：US06046108A

    公开(公告)日：2000-04-04

    申请号：US344402

    申请日：1999-06-25

    申请人： Chung-Shi Liu ,  Chen-Hua Yu ,  Tien-I Bao ,  Syun-Ming Jang

    发明人： Chung-Shi Liu ,  Chen-Hua Yu ,  Tien-I Bao ,  Syun-Ming Jang

    IPC分类号： H01L21/768 ,  H01L21/44

    CPC分类号： H01L21/76867 ,  H01L21/7684 ,  H01L21/76849

    摘要： Form a dielectric layer on a surface of a conductive substrate with a trench through the top surface down to the substrate. Form a barrier layer over the dielectric layer including the exposed surface of the conductive substrate and the exposed sidewalls of the dielectric layer. Form a copper conductor over the barrier layer and overfilling the narrow hole in the trench. Etch away material from the surface of the copper conductor by a CMP process lowering the copper leaving a thin layer of copper over the barrier layer above the dielectric layer aside from the hole. Form a copper passivation by combining an element selected from silicon and germanium with copper on the exposed surfaces of the copper surfaces forming an interface in the narrower hole between the copper and the copper compound located below the dielectric top level. Etch away material from the surface of the copper compound and the barrier layer to planiarize the copper compound by etching down to the dielectric top level leaving a thin layer of the copper passivation compound covering the copper conductor in the narrower hole.

    摘要翻译： 在具有沟槽的导电基底的表面上形成电介质层，通过顶表面向下延伸到衬底。 在包括导电基底的暴露表面和电介质层暴露的侧壁的电介质层上形成阻挡层。 在阻挡层上形成一个铜导体，并且填充沟槽中的窄孔。 通过CMP工艺从铜表面蚀刻掉材料，在除了孔之外的电介质层之上的阻挡层上方，降低铜，从而留下薄的铜层。 通过将选自硅和锗的元素与铜的暴露表面上的铜组合形成铜钝化，在铜和化合物之间的较窄的孔中形成界面，位于电介质顶层之下。 从铜化合物的表面和阻挡层的表面蚀刻掉材料，以通过蚀刻到电介质顶层来平面化铜化合物，留下在较窄的孔中覆盖铜导体的铜钝化化合物的薄层。

    Use of a low resistivity Cu.sub.3 Ge interlayer as an adhesion promoter between copper and tin layers
    10.
    发明授权
    Use of a low resistivity Cu.sub.3 Ge interlayer as an adhesion promoter between copper and tin layers 失效
    使用低电阻率Cu3Ge中间层作为铜和锡层之间的粘合促进剂

    公开(公告)号：US6083829A

    公开(公告)日：2000-07-04

    申请号：US083419

    申请日：1998-05-22

    申请人： Jane-Bai Lai ,  Lih-Juann Chen ,  Chung-Shi Liu ,  Chen-Hua Douglas Yu

    发明人： Jane-Bai Lai ,  Lih-Juann Chen ,  Chung-Shi Liu ,  Chen-Hua Douglas Yu

    IPC分类号： C23C16/56 ,  C23C26/00 ,  C23C28/00 ,  H01L21/288 ,  H01L21/321 ,  H01L21/768 ,  H01L23/532 ,  H01L21/4763

    CPC分类号： H01L21/76873 ,  C23C16/56 ,  C23C26/00 ,  C23C28/00 ,  H01L21/2885 ,  H01L21/321 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/53238 ,  H01L2924/0002

    摘要： A method for fabricating a copper interconnect structure, using a low resistivity Cu.sub.3 Ge intermetallic layer, as an adhesive layer, has been developed. Following an in situ, CVD of a titanium nitride barrier layer, a germanium layer, and a copper layer, an anneal procedure is used to form the Cu.sub.3 Ge intermetallic layer, with the intermetallic layer, located between the underlying titanium nitride barrier layer, and the overlying copper layer. The Cu.sub.3 Ge intermetallic layer can also be formed in situ, during deposition, if the deposition temperature exceeds 150.degree. C. Cu.sub.3 Ge layer exhibits a resistivity of about 5E-6 ohm - cm. A second iteration of this invention allows a thick copper layer to be plated on a thin copper seed layer, only on the top surface of a semiconductor substrate. This iteration, also incorporating the low resistivity, Cu.sub.3 Ge intermetallic, and the adhesive layer, prevents copper from being plated on the beveled edge of the semiconductor substrate.

    摘要翻译： 已经开发了使用低电阻率Cu 3 Ge金属间化合物作为粘合剂层的铜互连结构的制造方法。 在原位，氮化钛阻挡层，锗层和铜层的CVD之后，使用退火程序形成Cu 3 Ge金属间化合物层，金属间层位于下面的氮化钛阻挡层和 上覆铜层。 如果沉积温度超过150℃，Cu3Ge金属间化合物层也可以在沉积过程中原位形成。Cu3Ge层的电阻率约为5E-6欧姆 - 厘米。 本发明的第二次迭代允许厚铜层仅在半导体衬底的顶表面上镀覆在薄铜籽晶层上。 也包含低电阻率Cu3Ge金属间化合物和粘合剂层的这种迭代防止铜电镀在半导体衬底的斜边上。