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16 条记录 (耗时 0.017 秒)

    Stencil mask and method of producing the same
    1.
    发明申请
    Stencil mask and method of producing the same 审中-公开
    模板面膜及其制造方法

    公开(公告)号：US20050100800A1

    公开(公告)日：2005-05-12

    申请号：US10983708

    申请日：2004-11-09

    申请人： Tadahiko Hirakawa ,  Hiroshi Kumano

    发明人： Tadahiko Hirakawa ,  Hiroshi Kumano

    IPC分类号： H01L21/266 ,  G03F1/20 ,  H01L21/027 ,  H01L21/265 ,  G03F9/00 ,  G03C5/00

    CPC分类号： G03F1/20 ,  H01J2237/31711

    摘要： To provide a stencil mask that contamination generating because a material layer set in the surface of a stencil mask is sputtered by a charged particle beam can be-prevented and a method of producing the same. A stencil mask has a thin film having an aperture pattern and a method of producing the same, and a stencil mask and the method of producing the same has an aspect that a material layer having heat conductance higher than that of a thin film is set in the region except for a portion of outer edge of the aperture pattern in the side of a principal surface of a thin film.

    摘要翻译： 为了提供一种模板掩模，可以防止由于通过带电粒子束溅射设置在模板掩模的表面中的材料层而产生的污染物及其制造方法。 模板掩模具有具有孔径图案的薄膜及其制造方法，并且模板掩模及其制造方法具有将导热率高于薄膜的材料层设置在 除了在薄膜的主表面侧的孔图案的外边缘的一部分之外的区域。

    Stencil mask and method of producing the same
    2.
    发明申请
    Stencil mask and method of producing the same 审中-公开
    模板面膜及其制造方法

    公开(公告)号：US20050100801A1

    公开(公告)日：2005-05-12

    申请号：US10983726

    申请日：2004-11-09

    申请人： Tadahiko Hirakawa ,  Hiroshi Kumano

    发明人： Tadahiko Hirakawa ,  Hiroshi Kumano

    IPC分类号： G03F1/20 ,  H01L21/027 ,  H01L21/266 ,  H01L21/302 ,  H01L23/12 ,  G03F9/00 ,  G03C5/00

    CPC分类号： G03F1/20 ,  H01J2237/31711

    摘要： To provide a stencil mask that the heat generated in the surface of the stencil mask can be radiated to a supporting substrate supporting a portion around the edge of a thin film quickly and a method of producing the same. A stencil mask has a thin film having an aperture pattern and a supporting substrate supporting a portion around the edge of a thin film and a method of producing the same, and a stencil mask and the method of producing the same has an aspect that a plug that having heat conductance higher than that of a thin film and a supporting substrate is embedded in a state of contacting a thin film and reaches inside of a supporting substrate.

    摘要翻译： 为了提供一种模版掩模，可以将模板掩模表面产生的热量迅速地辐射到支撑薄膜边缘附近的支撑基板上，以及制造该模板的方法。 模板掩模具有具有孔径图案的薄膜和支撑薄膜边缘周围的部分的支撑基板及其制造方法，并且模板掩模及其制造方法具有以下方面：插头 具有高于薄膜和支撑衬底的导热性的薄膜被嵌入到接触薄膜并到达支撑衬底内部的状态。

    Lead alloy for lead-acid batteries and process for producing the alloy
    3.
    发明授权
    Lead alloy for lead-acid batteries and process for producing the alloy 失效
    铅酸蓄电池铅合金及合金制造工艺

    公开(公告)号：US4207097A

    公开(公告)日：1980-06-10

    申请号：US969556

    申请日：1978-12-14

    申请人： Sadao Fukuda ,  Hidemi Fukunaga ,  Hiroshi Kumano

    发明人： Sadao Fukuda ,  Hidemi Fukunaga ,  Hiroshi Kumano

    IPC分类号： C22C11/06 ,  H01M4/68

    CPC分类号： H01M4/685 ,  C22C11/06

    摘要： An alloy consisting predominantly of lead and containing 0.1 to 3.0% by weight of tin, 0.1 to 0.3% by weight of arsenic and 0.01 to 0.1% by weight of aluminum or copper. The alloy may further contain 0.002 to 1.0% by weight of cadmium. The alloy is useful for grids, inter-cell connectors and poles to provide lead-acid batteries less prone to self-discharge and capable of withstanding over discharge.

    摘要翻译： 主要由铅组成并含有0.1〜3.0重量％的锡，0.1〜0.3重量％的砷和0.01〜0.1重量％的铝或铜的合金。 该合金还可以含有0.002〜1.0重量％的镉。 该合金可用于网格，电池间连接器和电极，以提供不容易自放电并能够承受过放电的铅酸电池。

    SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF REALIZING REDUCTION IN SIZE
    4.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF REALIZING REDUCTION IN SIZE 审中-公开
    具有实现减小尺寸的半导体集成电路

    公开(公告)号：US20080099874A1

    公开(公告)日：2008-05-01

    申请号：US11923132

    申请日：2007-10-24

    申请人： Hiroshi Kumano

    发明人： Hiroshi Kumano

    IPC分类号： H01L29/00

    CPC分类号： H01L21/76286

    摘要： In a semiconductor integrated circuit in which an element isolating insulation film is provided on a substrate, an isolated Si region in the substrate is a shape composed of straight lines which form four sides and circular arcs which form four corners. Further, the adjacent Si regions share element isolating insulation films, and the adjacent Si regions are separated by one element isolating insulation film. Furthermore, widths of the element isolating insulation films are the same in a chip pattern. When the width of the element isolating insulation film is set to a, and a curvature radius of curved lines at four corners of the Si region is set to r; the width a and the curvature radius r are determined so as to satisfy conditions of r>0.7a in the case where the element isolating insulation films are intersected only in a cross shape, and r>1.5a in the case where the element isolating insulation films include a portion intersected in a T shape.

    摘要翻译： 在基板上设置有元件隔离绝缘膜的半导体集成电路中，基板中的隔离Si区域由形成四个边的直线和形成四个角的圆弧构成。 此外，相邻的Si区域共享元件隔离绝缘膜，并且相邻的Si区域被一个元件隔离绝缘膜隔开。 此外，元件隔离绝缘膜的宽度在芯片图案中是相同的。 当元件隔离绝缘膜的宽度设定为a，将Si区域的四个角部的曲线的曲率半径设定为r时， 在元件隔离绝缘膜仅交叉形状的情况下，宽度a和曲率半径r被确定为满足r> 0.7a的条件，并且在元件隔离绝缘 膜包括以T形交叉的部分。

    Silver oxide primary cell
    7.
    发明授权
    Silver oxide primary cell 失效
    氧化银原电池

    公开(公告)号：US4387143A

    公开(公告)日：1983-06-07

    申请号：US127518

    申请日：1980-03-05

    申请人： Tomohiko Arita ,  Kaoru Murakami ,  Mitsugu Okahisa ,  Hiroshi Kumano

    发明人： Tomohiko Arita ,  Kaoru Murakami ,  Mitsugu Okahisa ,  Hiroshi Kumano

    IPC分类号： H01M4/06 ,  H01M6/12 ,  H01M2/26

    CPC分类号： H01M6/12

    摘要： The disclosure relates to a silver oxide primary cell which includes a casing composed of a positive electrode container and a negative electrode container to define a sealed chamber between them, a positive electrode, an insulating layer, a negative electrode, a separator member, an electrically conductive member, and an insulating gasket housed in the sealed chamber.The electrically conductive member is pressed, at its portion protruding toward peripheral edge portion of the positive electrode, against the bottom face of the positive electrode container by the insulating gasket, and is simultaneously electrically connected to the bottom face or side wall of the positive electrode container.

    摘要翻译： 本发明涉及一种氧化银原子电池，其包括由正极容器和负极容器组成的壳体，以在其间限定密封室，正极，绝缘层，负极，隔板构件，电 导电构件和容纳在密封室中的绝缘垫圈。 导电部件在其正极的周边部分突出的部分被绝缘垫片压靠在正极容器的底面上，同时电连接到正极的底面或侧壁 容器。

    Semiconductor device and fabrication method thereof
    10.
    发明授权
    Semiconductor device and fabrication method thereof 有权
    半导体器件及其制造方法

    公开(公告)号：US08692315B2

    公开(公告)日：2014-04-08

    申请号：US13403313

    申请日：2012-02-23

    申请人： Hiroshi Kumano

    发明人： Hiroshi Kumano

    IPC分类号： H01L27/088 ,  H01L21/336

    CPC分类号： H01L27/092 ,  H01L21/743 ,  H01L23/535 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/36 ,  H01L29/732 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a semiconductor substrate having an active layer in which an element region and a contact region are formed, a support substrate supporting the active layer, and a buried insulation layer interposed between the active layer and the support substrate. A transistor element is formed in the element region, the transistor element having a transistor buried impurity layer formed within the active layer. The semiconductor device further includes a substrate contact having a contact buried impurity layer formed within the contact region and a through contact extending from the surface of the active layer to the support substrate through the contact buried impurity and the buried insulation layer, the contact buried impurity layer being in the same layer as the transistor buried impurity layer.

    摘要翻译： 半导体器件包括具有其中形成有元件区域和接触区域的有源层的半导体衬底，支撑有源层的支撑衬底以及置于有源层和支撑衬底之间的掩埋绝缘层。 晶体管元件形成在元件区域中，晶体管元件具有在有源层内形成的晶体管埋入杂质层。 半导体器件还包括具有在接触区域内形成的接触掩埋杂质层的基片接触件和通过接触掩埋杂质和掩埋绝缘层从有源层表面延伸到支撑基板的通孔，接触掩埋杂质 层位于与晶体管埋入杂质层相同的层中。