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    Semiconductor devices having substrate plug and methods of forming the same
    1.
    发明申请
    Semiconductor devices having substrate plug and methods of forming the same 审中-公开
    具有基板插头的半导体器件及其形成方法

    公开(公告)号：US20080073717A1

    公开(公告)日：2008-03-27

    申请号：US11785676

    申请日：2007-04-19

    申请人： Tae-Hong Ha ,  Jong-Mil Youn ,  Hoon Lim ,  Hoo-Sung Cho ,  Jae-Hun Jeong

    发明人： Tae-Hong Ha ,  Jong-Mil Youn ,  Hoon Lim ,  Hoo-Sung Cho ,  Jae-Hun Jeong

    IPC分类号： H01L27/06 ,  H01L21/02

    CPC分类号： H01L27/0688 ,  H01L21/743

    摘要： A semiconductor device includes a device isolation layer disposed in a substrate and defining an active region, a first gate pattern on the active region, a first insulating layer on the substrate and the first gate pattern, a first body region on the first insulating layer, and a first substrate plug extending from the substrate into the first insulating layer, the first substrate plug penetrating the device isolation layer and contacting the substrate under the device isolation layer.

    摘要翻译： 半导体器件包括设置在衬底中并限定有源区的器件隔离层，有源区上的第一栅极图案，衬底上的第一绝缘层和第一栅极图案，第一绝缘层上的第一体区， 以及从所述基板延伸到所述第一绝缘层中的第一基板插塞，所述第一基板插塞穿透所述器件隔离层并且在所述器件隔离层下面接触所述基板。

    Electrostatic discharge protection devices
    2.
    发明授权
    Electrostatic discharge protection devices 有权

    公开(公告)号：US10153270B2

    公开(公告)日：2018-12-11

    申请号：US14599593

    申请日：2015-01-19

    申请人： Dae-Lim Kang ,  Hyun-Jo Kim ,  Jong-Mil Youn ,  Soo-Hun Hong

    发明人： Dae-Lim Kang ,  Hyun-Jo Kim ,  Jong-Mil Youn ,  Soo-Hun Hong

    IPC分类号： H01L27/02 ,  H01L27/088 ,  H01L29/16 ,  H01L29/08

    摘要： An ESD protection device includes a substrate having an active fin extending in a first direction, a plurality of gate structures extending in a second direction at a given angle with respect to the first direction and partially covering the active fin, an epitaxial layer in a recess on a portion of the active fin between the gate structures, an impurity region under the epitaxial layer, and a contact plug contacting the epitaxial layer. A central portion of the impurity region is thicker than an edge portion of the impurity region, in the first direction. The contact plug lies over the central portion of the impurity region.

    Method for fabricating a BiCMOS device
    3.
    发明授权
    Method for fabricating a BiCMOS device 失效
    BiCMOS器件制造方法

    公开(公告)号：US4950616A

    公开(公告)日：1990-08-21

    申请号：US353105

    申请日：1989-05-17

    申请人： Chang-Won Kahng ,  Sung-Ki Min ,  Jong-Mil Youn

    发明人： Chang-Won Kahng ,  Sung-Ki Min ,  Jong-Mil Youn

    IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/68 ,  H01L29/70

    CPC分类号： H01L21/763 ,  Y10S148/009

    摘要： This invention provides a method for fabricating a semiconductor device comprising the steps of forming buried layers on the silicon substrate; etching an epitaxial layer after said layer is grown up, the step further including the processes of etching selectively the silicon epitaxial layer of well region on which a high speed bipolar transistor is formed to be thin and keeping the silicon epitaxial layer of well region on which nMOS transistor is formed remained the same thickness as grown up; and forming a pMOS transistor, a nMOS transistor and a bipolar transistor. High efficiency and high integration is easily attained in fabricating the high speed bipolar transistor and high performance CMOS transistor on same chip and by reducing the difficulty in processing according to the method of present invention.

    摘要翻译： 本发明提供一种制造半导体器件的方法，包括以下步骤：在硅衬底上形成掩埋层; 在所述层生长之后蚀刻外延层，该步骤还包括选择性地蚀刻其上形成有高速双极晶体管的阱区的硅外延层的工艺，并保持其上的阱区的硅外延层 形成的nMOS晶体管的长度保持相同的厚度; 以及形成pMOS晶体管，nMOS晶体管和双极晶体管。 在同一芯片上制造高速双极晶体管和高性能CMOS晶体管并且通过降低根据本发明的方法的处理难度，容易实现高效率和高集成度。

    Ternary content addressable memory cell
    6.
    发明授权
    Ternary content addressable memory cell 有权
    三进制内容可寻址存储单元

    公开(公告)号：US07112831B2

    公开(公告)日：2006-09-26

    申请号：US10841775

    申请日：2004-05-06

    申请人： Jin-Ho Kim ,  Jong-Mil Youn ,  Bong-Hyun Choi

    发明人： Jin-Ho Kim ,  Jong-Mil Youn ,  Bong-Hyun Choi

    IPC分类号： H01L27/10 ,  H01L29/7694 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L27/11 ,  G11C15/04 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/1104 ,  Y10S257/903

    摘要： Ternary CAM cells are provided. The ternary CAM cell includes a pair of half cells. Each of the half cells includes an isolation layer formed at a predetermined region of a semiconductor substrate to define a match cell active region. A search gate electrode and a node gate electrode are placed to cross over the match cell active region. A match line is electrically connected to the match cell active region, which is adjacent to the node gate electrode and is located opposite the search gate electrode. An SRAM cell is provided at the semiconductor substrate adjacent to the match cell active region. The node gate electrode is electrically connected to one of a pair of storage nodes of the SRAM cell.

    摘要翻译： 提供三元CAM单元。 三元CAM单元包括一对半单元。 每个半单元包括形成在半导体衬底的预定区域处以限定匹配单元有源区的隔离层。 搜索栅电极和节点栅电极被放置成跨越匹配单元有源区。 匹配线电连接到与节点栅电极相邻并且与搜索栅电极相对的匹配单元有源区。 SRAM单元设置在与匹配单元有源区相邻的半导体衬底处。 节点栅极电连接到SRAM单元的一对存储节点之一。

    CMOS static random access memory devices
    7.
    发明授权
    CMOS static random access memory devices 有权
    CMOS静态随机存取存储器件

    公开(公告)号：US6147385A

    公开(公告)日：2000-11-14

    申请号：US218819

    申请日：1998-12-22

    申请人： Sung-Bong Kim ,  Ki-Joon Kim ,  Jong-Mil Youn

    发明人： Sung-Bong Kim ,  Ki-Joon Kim ,  Jong-Mil Youn

    IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

    CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903

    摘要： A full CMOS SRAM cell having the capability of having a reduced aspect ratio is described. The SRAM cell includes first and second transfer transistors of n-channel types, first and second driving transistors of the n-channel types and first and second load transistors of p-channel types. Each of the transistors has source and drain regions on opposite sides of a channel region formed in a semiconductor substrate and a gate over the channel region. The cell includes a first common region defined by the drain regions of the first transfer transistor and the first driving transistor connected in series therethrough. A second common region is defined by the drain regions of the second transfer transistor and the second driving transistor connected in series therethrough. The drain region of the first load transistor is disposed adjacent to the first common region between the first and second common regions. The drain region of the second load transistor is disposed between the drain region of the first load transistor and the second common region. First and second gate electrode layers are disposed generally parallel to each other, and respectively serving as the gates of the first driving transistor and the first load transistor and as the gates of the second driving transistor and the second load transistor, wherein each of the first and second gate electrode layers is made of a conductive material of a first level. First and second interconnecting layers are each made of a conductive material of a second level different from the first level, the first interconnecting layer connecting the first common region to the drain region of the first load transistor and the second gate electrode layer, the second interconnecting layer connecting the second common region to the drain region of the second load transistor and the first gate electrode layer.

    摘要翻译： 描述具有减小的纵横比的能力的完整CMOS SRAM单元。 SRAM单元包括n沟道类型的第一和第二传输晶体管，n沟道类型的第一和第二驱动晶体管以及p沟道类型的第一和第二负载晶体管。 每个晶体管在形成在半导体衬底中的沟道区的相对侧上具有源极和漏极区域，并且在沟道区域上具有栅极。 单元包括由第一传输晶体管的漏极区域和串联连接的第一驱动晶体管限定的第一公共区域。 第二公共区域由第二传输晶体管和串联连接的第二驱动晶体管的漏极区限定。 第一负载晶体管的漏极区域设置成与第一和第二公共区域之间的第一公共区域相邻。 第二负载晶体管的漏极区域设置在第一负载晶体管的漏极区域和第二公共区域之间。 第一和第二栅极电极层大体上彼此平行地设置，并且分别用作第一驱动晶体管和第一负载晶体管的栅极，以及作为第二驱动晶体管和第二负载晶体管的栅极，其中第一 并且第二栅电极层由第一级的导电材料制成。 第一和第二互连层各自由不同于第一电平的第二电平的导电材料制成，第一互连层将第一公共区域连接到第一负载晶体管的漏极区域和第二栅极电极层，第二互连 将第二公共区域连接到第二负载晶体管的漏极区域和第一栅极电极层的层。

    Method of fabricating a semiconductor device
    10.
    发明授权
    Method of fabricating a semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US4912055A

    公开(公告)日：1990-03-27

    申请号：US265420

    申请日：1988-10-31

    申请人： Sung-Ki Min ,  Chang-Won Kahng ,  Uk-Rae Cho ,  Jong-Mil Youn ,  Suk-Gi Choi

    发明人： Sung-Ki Min ,  Chang-Won Kahng ,  Uk-Rae Cho ,  Jong-Mil Youn ,  Suk-Gi Choi

    IPC分类号： H01L29/73 ,  C08G18/30 ,  C08G18/32 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/08 ,  H01L27/10 ,  H01L29/732

    CPC分类号： H01L21/8249

    摘要： A method for fabricating a BiCMOS device to achieve a maximum performance through a of minimum processing steps, in which the BiCMOS device is exemplary for its high integration and high performance MOS transistors, self-aligned metal contact emitter type bipolar transistors having high load driving force, high performance matching characteristics and high integration, and self-aligned polycrystalline silicon emitter type bipolar transistors having high integration and high speed characteristics in low current, thereby being used in high integration, high speed digital and precise analog system. The method includes a plurality of fabrication steps including ion-implantation, formation of a thin film oxide layer, deposition of a nitride layer, etching of the oxide layer, formation of windows and others, alternately and/or sequentially in a single chip substrate.

    摘要翻译： 一种用于制造BiCMOS器件以通过最小处理步骤实现最大性能的方法，其中BiCMOS器件是其高集成度和高​​性能MOS晶体管的示例性，具有高负载驱动力的自对准金属接触发射极型双极晶体管 ，高性能匹配特性和高集成度，以及在低电流下具有高集成度和高​​速特性的自对准多晶硅发射极型双极晶体管，从而被用于高集成度，高速数字和精确模拟系统。 该方法包括在单个芯片衬底中交替地和/或顺序地包括离子注入，薄膜氧化物层的形成，氮化物层的沉积，氧化物层的蚀刻，窗口等的形成的多个制造步骤。