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    Conductor layout technique to reduce stress-induced void formations
    3.
    发明授权
    Conductor layout technique to reduce stress-induced void formations 有权
    导体布置技术，以减少应力引起的空隙形成

    公开(公告)号：US08435802B2

    公开(公告)日：2013-05-07

    申请号：US11438127

    申请日：2006-05-22

    申请人： Min-Hwa Chi ,  Tai-Chun Huang ,  Chih-Hsiang Yao

    发明人： Min-Hwa Chi ,  Tai-Chun Huang ,  Chih-Hsiang Yao

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76898 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device.

    摘要翻译： 通过退火工艺制备半导体器件，通过由绝缘体材料包围的导体线来互连器件的至少两个部件。 退火过程导致在导线和绝缘体材料内形成残余应力。 在掩模的选择性部分上的布局中设计凹口，用于图案化导体线。 选择部分上的凹口形状的存在在不存在凹口的情况下，在导线内产生额外的应力分量。 选择凹口的位置使得额外的应力分量基本上抵消残余应力，从而导致残余应力的净减小。 残余应力的减小导致相应的机械应力迁移，从而提高了装置的可靠性。