公开(公告)号：US20240332356A1

公开(公告)日：2024-10-03

申请号：US18193445

申请日：2023-03-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H01L29/06 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/0673 ,  H01L21/823807 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

摘要： A device includes a stack of first nanostructures, wherein each first nanostructure includes a channel region with a first width; a first gate on the stack of first nanostructures, wherein each first nanostructure is surrounded by the first gate, wherein a distance from a first end of the first gate to an adjacent first nanostructure is a first distance; a stack of second nanostructures, wherein each second nanostructure includes a channel region with a second width greater than the first width; a second gate on the stack of second nanostructures, wherein each second nanostructure is surrounded by the second gate, wherein a second distance from a first end of the second gate to an adjacent second nanostructure is greater than the first distance; and a first isolation structure extending continuously from the first end of the first gate to the first end of the second gate.

公开(公告)号：US12106801B2

公开(公告)日：2024-10-01

申请号：US17858376

申请日：2022-07-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： G11C11/412 ,  G11C11/419 ,  G11C5/02 ,  G11C7/10 ,  G11C7/12

CPC分类号： G11C11/419 ,  G11C11/412 ,  G11C5/025 ,  G11C7/1096 ,  G11C7/12

摘要： An array of memory cells is arranged into a plurality of columns and rows. A first signal line extends through a first column of the plurality of columns. The first signal line is electrically coupled to the memory cells in the first column. A first end portion of the first signal line is configured to receive a logic high signal from a first circuit during a first operational state of the memory device and a logic low signal from the first circuit during a second operational state of the memory device. A second circuit includes a plurality of transistors. The transistors are configured to be turned on or off to electrically couple a second end portion of the first signal line to a logic low source when the first end portion of the first signal line is configured to receive the logic low signal from the first circuit.

公开(公告)号：US20240321958A1

公开(公告)日：2024-09-26

申请号：US18187233

申请日：2023-03-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Lung Tung ,  Xiaodong Wang ,  Jhon Jhy Liaw

IPC分类号： H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/0673 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： In an embodiment, a method includes: placing a first cell in a device layout, the first cell defining a first transistor, the first transistor including a first quantity of first nanostructures; placing a second cell in the device layout directly adjacent to the first cell, the second cell defining a second transistor, the second transistor including a second quantity of second nanostructures, the second quantity being different than the first quantity; generating a lithography mask based on the device layout; and manufacturing a semiconductor device using the lithography mask.

公开(公告)号：US12074057B2

公开(公告)日：2024-08-27

申请号：US18057688

申请日：2022-11-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC分类号： H01L21/762 ,  G06F30/392 ,  H01L21/84 ,  H01L29/06

CPC分类号： H01L21/76283 ,  H01L21/845 ,  H01L29/0649 ,  G06F30/392

摘要： Semiconductor structures and methods are provided. A semiconductor structure according to an embodiment includes a first cell disposed over a first well doped with a first-type dopant, a second cell disposed over the first well, and a tap cell disposed over the first well. The tap cell is sandwiched between the first cell and the second cell. The first cell includes a first plurality of transistors and the second cell includes a second plurality of transistors.

公开(公告)号：US20240006513A1

公开(公告)日：2024-01-04

申请号：US18469336

申请日：2023-09-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/6656 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/785 ,  H01L2029/7858

摘要： A semiconductor device according to the present disclosure includes a first channel member including a first channel portion and a first connection portion, a second channel member including a second channel portion and a second connection portion, a gate structure disposed around the first channel portion and the second channel portion, and an inner spacer feature disposed between the first connection portion and the second connection portion. The gate structure includes a gate dielectric layer and a gate electrode. The gate dielectric layer extends partially between the inner spacer feature and the first connection portion and between the inner spacer feature and the second connection portion. The gate electrode does not extend between the inner spacer feature and the first connection portion and between the inner spacer feature and the second connection portion.

公开(公告)号：US20230395601A1

公开(公告)日：2023-12-07

申请号：US18447407

申请日：2023-08-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L27/0924 ,  H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/1037 ,  H01L29/0847

摘要： The present disclosure provides an integrated circuit device that comprises a semiconductor substrate having a top surface; a first and a second source/drain features over the semiconductor substrate; a first semiconductor layer extending in parallel with the top surface and connecting the first and the second source/drain features, the first semiconductor layer having a center portion and two end portions, each of the two end portions connecting the center portion and one of the first and second source/drain features; a first spacer over the two end portions of the first semiconductor layer; a second spacer vertically between the two end portions of the first semiconductor layer and the top surface; and a gate electrode wrapping around and engaging the center portion of the first semiconductor layer. The center portion has a thickness smaller than the two end portions.

公开(公告)号：US20230369459A1

公开(公告)日：2023-11-16

申请号：US18360681

申请日：2023-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/6656 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0928 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： The present disclosure provides a semiconductor device and a method of forming the same. In an embodiment, the semiconductor device includes a fin extending from a substrate, a gate structure over the channel region, a first spacer extending along a sidewall of the lower portion of the gate structure, and a second spacer extending along a sidewall of the upper portion of the gate structure. The fin includes a channel region and a source/drain (S/D) region adjacent to the channel region. The gate structure includes an upper portion and a lower portion. The second spacer is disposed on a top surface of the first spacer. The first spacer is formed of a first dielectric material and the second spacer is formed of a second dielectric material different from the first dielectric material.

公开(公告)号：US20230369434A1

公开(公告)日：2023-11-16

申请号：US18357761

申请日：2023-07-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jhon Jhy Liaw

IPC分类号： H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06 ,  H01L29/10 ,  H01L27/02

CPC分类号： H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/495 ,  H10B10/12 ,  H01L29/0673 ,  H01L29/1033 ,  H01L27/0207 ,  H10B10/18

摘要： An exemplary semiconductor memory chip includes a first static random access memory (SRAM) cell and a second SRAM cell. The first SRAM cell has a first GAA transistor, and the second SRAM cell has a second GAA transistor. The first and the second SRAM cells have a same cell size, and the first and the second GAA transistors are of a same transistor type. Moreover, the first GAA transistor has a first threshold voltage and the second GAA transistor has a second threshold voltage. The second threshold voltage is different than the first threshold voltage. Furthermore, the first GAA transistor has a first gate stack and the second GAA transistor has a second gate stack. The first gate stack has a first work function value, and the second gate stack has a second work function value. The second work function value is different than the first work function value.

公开(公告)号：US11784180B2

公开(公告)日：2023-10-10

申请号：US17373302

申请日：2021-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/762 ,  H01L29/45 ,  H01L29/51 ,  H01L29/49 ,  H01L29/167 ,  H01L29/165 ,  H01L29/78 ,  H01L29/08 ,  H01L21/3105

CPC分类号： H01L27/0207 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/0928 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66545 ,  H01L21/31053 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7848

摘要： Semiconductor devices and semiconductor cell arrays are provided herein. In some examples, a semiconductor device includes a multi-fin active region, a mono-fin active region, and an isolation feature between the multi-fin active region and the mono-fin active region. The multi-fin active region includes a first plurality of fins, a second plurality of fins parallel to the first plurality of fins, a first n-type field effect transistor (FET), and a first p-type FET. The mono-fin active region abuts the multi-fin active region. The mono-fin active region includes a first fin, a second fin different from the first fin, a second n-type FET, and a second p-type FET. The isolation feature is parallel to the first and second gate structures.

公开(公告)号：US11742349B2

公开(公告)日：2023-08-29

申请号：US17717296

申请日：2022-04-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Shien-Yang Wu

IPC分类号： H01L21/00 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

CPC分类号： H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

摘要： A method includes forming a first channel region, a second channel region, and a third channel region over a substrate, depositing a first interfacial layer over the first, second, and third channel regions, removing the first interfacial layer from the first and second channel regions, depositing a second interfacial layer over the first and second channel regions, thinning a thickness of the second interfacial layer over the first channel region, depositing a high-k dielectric layer over the first, second, and third channel regions, and forming a gate electrode layer over the first, second, and third channel regions.