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公开(公告)号：US11380580B2
公开(公告)日：2022-07-05
申请号：US17007260
申请日：2020-08-31
IPC分类号： H01L21/768 , G11C5/06 , H01L21/3213 , G11C11/16
摘要： The present disclosure relates to a method of forming an integrated chip. The method includes forming a memory device over a substrate and forming an etch stop layer over the memory device. An inter-level dielectric (ILD) layer is formed over the etch stop layer and laterally surrounding the memory device. One or more patterning process are performed to define a first trench extending from a top of the ILD layer to expose an upper surface of the etch stop layer. A removal process is performed to remove an exposed part of the etch stop layer. A conductive material is formed within the interconnect trench after performing the removal process.
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公开(公告)号：US11121308B2
公开(公告)日：2021-09-14
申请号：US16601723
申请日：2019-10-15
发明人： Yao-Wen Chang , Chung-Chiang Min , Harry-Hak-Lay Chuang , Hung Cho Wang , Tsung-Hsueh Yang , Yuan-Tai Tseng , Sheng-Huang Huang , Chia-Hua Lin
摘要： Various embodiments of the present disclosure are directed towards an integrated chip including a magnetoresistive random access memory (MRAM) cell over a substrate. A dielectric structure overlies the substrate. The MRAM cell is disposed within the dielectric structure. The MRAM cell includes a magnetic tunnel junction (MTJ) sandwiched between a bottom electrode and a top electrode. A conductive wire overlies the top electrode. A sidewall spacer structure continuously extends along a sidewall of the MTJ and the top electrode. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different than the first material.
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公开(公告)号：US09799665B2
公开(公告)日：2017-10-24
申请号：US15603923
申请日：2017-05-24
IPC分类号： H01L27/115 , H01L27/11521 , H01L29/66 , H01L29/423 , H01L29/06 , H01L27/11519 , H01L21/762 , H01L21/28 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/76224 , H01L21/76232 , H01L27/11519 , H01L29/0649 , H01L29/42328 , H01L29/66825 , H01L29/7881
摘要： A method for forming a semiconductor device structure is provided. The method includes forming a mask layer over a substrate. The method includes forming a first isolation structure and a second isolation structure passing through the mask layer and penetrating into the substrate. The method includes thinning the mask layer to expose a first portion of the first isolation structure and a second portion of the second isolation structure. The method includes partially removing the first portion, the second portion, the third portion, and the fourth portion. The method includes removing the thinned mask layer. The method includes forming a first gate over the substrate and between the first isolation structure and the second isolation structure. The method includes forming a dielectric layer over the first gate. The method includes forming a second gate over the dielectric layer and above the first gate.
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公开(公告)号：US09673204B2
公开(公告)日：2017-06-06
申请号：US14584735
申请日：2014-12-29
IPC分类号： H01L27/115 , H01L27/11521 , H01L29/06 , H01L21/762 , H01L29/66 , H01L21/28 , H01L29/423 , H01L27/11519 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/76224 , H01L21/76232 , H01L27/11519 , H01L29/0649 , H01L29/42328 , H01L29/66825 , H01L29/7881
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure also includes a first isolation structure partially embedded in the substrate. The first isolation structure has a first upper surface with a first recess. The semiconductor device structure further includes a second isolation structure partially embedded in the substrate. In addition, the semiconductor device structure includes a first gate over the substrate and between the first isolation structure and the second isolation structure. The first gate extends onto the first upper surface to cover the first recess. The semiconductor device structure includes a second gate over the first gate.
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公开(公告)号：US20160086965A1
公开(公告)日：2016-03-24
申请号：US14493568
申请日：2014-09-23
IPC分类号： H01L27/115
CPC分类号： H01L29/42344 , H01L27/1157 , H01L29/792
摘要： The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has cuboid shaped memory gate and select gate covered upper surfaces by some spacers. Thus the memory gate and select gate are protected from silicide. The memory gate and select gate are defined self-aligned by the said spacers. The memory gate and select gate are formed by etching back corresponding conductive materials not covered by the spacers instead of recess processes. Thus the memory gate and select gate have planar upper surfaces and are well defined. The disclosed device and method is also capable of further scaling since photolithography processes are reduced.
摘要翻译： 本公开涉及自对准分离门存储器单元及其相关方法。 自对准分离栅极存储单元具有立方形形状的存储栅极，并且通过一些间隔物选择栅极覆盖的上表面。 因此，存储器栅极和选择栅极被保护以防止硅化物。 存储器栅极和选择栅极被所述间隔物自对准地限定。 存储栅极和选择栅极通过蚀刻不被间隔物覆盖的相应导电材料而不是凹陷工艺而形成。 因此，存储器栅极和选择栅极具有平坦的上表面并且被明确定义。 所公开的装置和方法还能够进一步缩放，因为光刻工艺被减少。
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公开(公告)号：US10355011B2
公开(公告)日：2019-07-16
申请号：US15855940
申请日：2017-12-27
IPC分类号： H01L21/28 , H01L29/34 , H01L29/49 , H01L29/66 , H01L29/78 , H01L21/768 , H01L23/528 , H01L29/423 , H01L29/788 , H01L27/11521 , H01L27/11568
摘要： Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a control gate over a substrate and forming a dielectric layer covering the control gate. The method further includes forming a conductive layer having a first portion and a second portion over the dielectric layer. In addition, the first portion of the conductive layer is separated from the control gate by the dielectric layer. The method further includes forming an oxide layer on a top surface of the first portion of the conductive layer and removing the second portion of the conductive layer to form a memory gate.
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公开(公告)号：US10276584B2
公开(公告)日：2019-04-30
申请号：US15408994
申请日：2017-01-18
IPC分类号： H01L21/28 , H01L29/08 , H01L29/66 , H01L21/033 , H01L21/265 , H01L21/311 , H01L21/321 , H01L21/768 , H01L29/423 , H01L29/792 , H01L21/3105 , H01L21/3213 , H01L27/11568
摘要： A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. In some embodiments, a semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.
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公开(公告)号：US09859295B2
公开(公告)日：2018-01-02
申请号：US15425647
申请日：2017-02-06
IPC分类号： H01L27/11568 , H01L29/49 , H01L29/423 , H01L21/28 , H01L21/768
CPC分类号： H01L27/11568 , H01L21/28 , H01L21/28273 , H01L21/28282 , H01L21/76805 , H01L23/528 , H01L27/11521 , H01L29/34 , H01L29/42324 , H01L29/4234 , H01L29/4916 , H01L29/66825 , H01L29/7831 , H01L29/788 , H01L29/7881 , H01L2924/0002 , H01L2924/00
摘要： Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a word line cell over a substrate and forming a dielectric layer over the word line cell. The method further includes forming a conductive layer over the dielectric layer and polishing the conductive layer until the dielectric layer is exposed. The method further includes forming an oxide layer on a top surface of the conductive layer and removing portions of the conductive layer not covered by the oxide layer to form a memory gate.
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公开(公告)号：US09564448B2
公开(公告)日：2017-02-07
申请号：US14718171
申请日：2015-05-21
IPC分类号： H01L29/788 , H01L21/283 , H01L27/115 , H01L29/78 , H01L21/28 , H01L29/34 , H01L29/423 , H01L29/66 , H01L23/528 , H01L29/49
CPC分类号： H01L27/11568 , H01L21/28 , H01L21/28273 , H01L21/28282 , H01L21/76805 , H01L23/528 , H01L27/11521 , H01L29/34 , H01L29/42324 , H01L29/4234 , H01L29/4916 , H01L29/66825 , H01L29/7831 , H01L29/788 , H01L29/7881 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a control gate formed over the substrate. The semiconductor device structure further includes a memory gate formed over the substrate and a first spacer formed on a sidewall of the memory gate. The semiconductor device structure further includes a contact formed over the memory gate, wherein a portion of the contact extends into the first spacer.
摘要翻译： 提供半导体器件结构。 半导体器件结构包括衬底和形成在衬底上的控制栅极。 半导体器件结构还包括形成在衬底上的存储器栅极和形成在存储器栅极的侧壁上的第一间隔物。 半导体器件结构还包括形成在存储器栅极上的触点，其中触点的一部分延伸到第一间隔物中。
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公开(公告)号：US20210351348A1
公开(公告)日：2021-11-11
申请号：US16866704
申请日：2020-05-05
发明人： Chern-Yow Hsu , Chung-Chiang Min , Shih-Chang Liu
摘要： A memory cell with hard mask insulator and its manufacturing methods are provided. In some embodiments, a memory cell stack is formed over a substrate having a bottom electrode layer, a resistance switching dielectric layer over the bottom electrode layer, and a top electrode layer over the resistance switching dielectric layer. A first insulating layer is formed over the top electrode layer. A first metal hard masking layer is formed over the first insulating layer. Then, a series of etch is performed to pattern the first metal hard masking layer, the first insulating layer, the top electrode layer and the resistance switching dielectric layer to form a first metal hard mask, a hard mask insulator, a top electrode, and a resistance switching dielectric.
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