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公开(公告)号:US11837587B2
公开(公告)日:2023-12-05
申请号:US17567169
申请日:2022-01-03
发明人: Wei-Yu Chen , An-Jhih Su , Chi-Hsi Wu , Der-Chyang Yeh , Li-Hsien Huang , Po-Hao Tsai , Ming-Shih Yeh , Ta-Wei Liu
IPC分类号: H01L25/10 , H01L23/48 , H01L23/00 , H01L23/31 , H01L21/768 , H01L25/00 , H01L21/56 , H01L21/683 , H01L23/538 , H01L25/065
CPC分类号: H01L25/105 , H01L21/561 , H01L21/563 , H01L21/568 , H01L21/6835 , H01L21/76802 , H01L23/3121 , H01L23/3142 , H01L23/481 , H01L23/5389 , H01L24/05 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/96 , H01L24/97 , H01L25/50 , H01L23/3128 , H01L24/48 , H01L25/0657 , H01L2221/68345 , H01L2221/68359 , H01L2224/211 , H01L2224/24145 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06527 , H01L2225/06548 , H01L2225/06568 , H01L2225/06586 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/1433 , H01L2924/1436 , H01L2924/181 , H01L2224/48091 , H01L2924/00014 , H01L2924/1436 , H01L2924/00012 , H01L2924/1433 , H01L2924/00012 , H01L2924/00014 , H01L2224/45099 , H01L2924/181 , H01L2924/00012
摘要: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
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公开(公告)号:US10720409B2
公开(公告)日:2020-07-21
申请号:US16051311
申请日:2018-07-31
发明人: Chen-Hua Yu , Der-Chyang Yeh , Hsien-Wei Chen , Li-Hsien Huang , Yueh-Ting Lin , Wei-Yu Chen , An-Jhih Su
IPC分类号: H01L25/065 , H01L25/04 , H01L23/00 , H01L23/373 , H01L25/10 , H01L25/00 , H01L23/538 , H01L23/498
摘要: In some embodiments, a device includes a thermal-electrical-mechanical (TEM) chip having a functional circuit, a first die attached to a first side of the TEM chip, and a first via on the first side of the TEM chip and adjacent to the first die, the first via being electrically coupled to the TEM chip. The device also includes a first molding layer surrounding the TEM chip, the first die and the first via, where an upper surface of the first die and an upper surface of the first via are level with an upper surface of the first molding layer. The device further includes a first redistribution layer over the upper surface of the first molding layer and electrically coupled to the first via and the first die.
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公开(公告)号:US10700026B2
公开(公告)日:2020-06-30
申请号:US16207832
申请日:2018-12-03
发明人: Hsien-Wei Chen , Li-Hsien Huang
摘要: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization.
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公开(公告)号:US20190363062A1
公开(公告)日:2019-11-28
申请号:US16532162
申请日:2019-08-05
发明人: Shuo-Mao Chen , Der-Chyang Yeh , Li-Hsien Huang
IPC分类号: H01L23/00 , H01L21/768 , H01L23/31 , H01L23/522 , H01L23/525 , H01L21/56 , H01L23/538
摘要: An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.
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公开(公告)号:US10304801B2
公开(公告)日:2019-05-28
申请号:US15396208
申请日:2016-12-30
发明人: Li-Hsien Huang , An-Jhih Su , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh
IPC分类号: H01L25/065 , H01L23/00 , H01L21/56 , H01L23/31 , H01L25/00
摘要: An embodiment package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, a conductive line electrically connecting a first conductive via to a second conductive via, the conductive line including a first segment over the first integrated circuit die and having a first width, and a second segment over the first integrated circuit die having a second width larger than the first width, the second segment extending over a first boundary between the first integrated circuit die and the encapsulant.
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公开(公告)号:US20190148171A1
公开(公告)日:2019-05-16
申请号:US16227697
申请日:2018-12-20
发明人: Hsien-Wei Chen , Der-Chyang Yeh , Li-Hsien Huang
摘要: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.
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公开(公告)号:US10163661B2
公开(公告)日:2018-12-25
申请号:US14788258
申请日:2015-06-30
发明人: Hsien-Wei Chen , Der-Chyang Yeh , Li-Hsien Huang
IPC分类号: H01L21/768 , H01L21/56 , H01L23/31 , H01L23/00
摘要: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.
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公开(公告)号:US20180331069A1
公开(公告)日:2018-11-15
申请号:US16043435
申请日:2018-07-24
发明人: Chen-Hua Yu , Li-Hsien Huang , Chi-Hsi Wu , Der-Chyang Yeh , Hsien-Wei Chen , An-Jhih Su , Hua-Wei Tseng
IPC分类号: H01L25/065 , H01L23/00 , H01L25/00 , H01L21/56
CPC分类号: H01L25/0652 , H01L21/563 , H01L21/565 , H01L24/19 , H01L24/20 , H01L25/50 , H01L2224/04105 , H01L2224/05147 , H01L2224/05166 , H01L2224/05184 , H01L2224/12105 , H01L2224/13014 , H01L2224/13016 , H01L2224/13024 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/97 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/19011 , H01L2224/83 , H01L2924/00012
摘要: An embodiment is a structure including a first die, a molding compound at least laterally encapsulating the first die, a first redistribution structure including metallization patterns extending over the first die and the molding compound, a first conductive connector comprising a solder ball and an under bump metallization coupled to the first redistribution structure, and an integrated passive device bonded to a first metallization pattern in the first redistribution structure with a micro bump bonding joint, the integrated passive device being adjacent the first conductive connector.
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公开(公告)号:US10115634B2
公开(公告)日:2018-10-30
申请号:US15214776
申请日:2016-07-20
发明人: Chen-Hua Yu , Cheng-Hung Chang , Ebin Liao , Chia-Lin Yu , Hsiang-Yi Wang , Chun Hua Chang , Li-Hsien Huang , Darryl Kuo , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号: H01L21/768 , H01L23/48 , H01L23/498 , H01L21/02 , H01L21/306 , H01L21/3105 , H01L21/321
摘要: A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner.
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10.
公开(公告)号:US20180053746A1
公开(公告)日:2018-02-22
申请号:US15366654
申请日:2016-12-01
发明人: Chen-Hua Yu , Der-Chyang Yeh , Hsien-Wei Chen , Li-Hsien Huang , Yueh-Ting Lin , Wei-Yu Chen , An-Jhih Su
IPC分类号: H01L25/065 , H01L23/373 , H01L25/10 , H01L25/00
摘要: In some embodiments, a device includes a thermal-electrical-mechanical (TEM) chip having a functional circuit, a first die attached to a first side of the TEM chip, and a first via on the first side of the TEM chip and adjacent to the first die, the first via being electrically coupled to the TEM chip. The device also includes a first molding layer surrounding the TEM chip, the first die and the first via, where an upper surface of the first die and an upper surface of the first via are level with an upper surface of the first molding layer. The device further includes a first redistribution layer over the upper surface of the first molding layer and electrically coupled to the first via and the first die.
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