公开(公告)号：US20130157430A1

公开(公告)日：2013-06-20

申请号：US13769650

申请日：2013-02-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yao-Wu Feng

IPC分类号： H01L29/66 ,  H01L21/22 ,  H01L21/265

CPC分类号： H01L29/66681 ,  H01L21/22 ,  H01L21/265 ,  H01L27/0259 ,  H01L29/0692 ,  H01L29/0839 ,  H01L29/0847 ,  H01L29/417 ,  H01L29/41758 ,  H01L29/66393 ,  H01L29/66659 ,  H01L29/7436 ,  H01L29/7835

摘要： Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well.

摘要翻译： 本发明的实施例涉及用于形成ESD装置的静电放电（ESD）装置和方法。 一个实施例是ESD保护装置，其包括：良好地布置在衬底中，n阱设置在衬底中;高压n阱（HVNW），其设置在衬底中的p阱和n阱之间;源极n +区域设置在 p阱以及设置在n阱中的多个漏极n +区域。

公开(公告)号：US08772092B2

公开(公告)日：2014-07-08

申请号：US13689187

申请日：2012-11-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yu-Chang Jong ,  Chun-Chien Tsai

IPC分类号： H01L21/332

CPC分类号： H01L27/0251 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7835

摘要： A method for forming an integrated circuit. The method includes forming a first guard ring around at least one transistor over a substrate, the first guard ring having a first type dopant. The method further includes forming a second guard ring around the first guard ring, the second guard ring having a second type dopant. The method includes forming a first doped region adjacent to the first guard ring, the first doped region having the second type dopant. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having the first type dopant, wherein the first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).

摘要翻译： 一种用于形成集成电路的方法。 该方法包括在衬底上围绕至少一个晶体管形成第一保护环，第一保护环具有第一类型的掺杂剂。 该方法还包括在第一保护环周围形成第二保护环，第二保护环具有第二类型掺杂剂。 该方法包括形成与第一保护环相邻的第一掺杂区域，第一掺杂区域具有第二类型掺杂剂。 该方法还包括形成与第二保护环相邻的第二掺杂区域，第二掺杂区域具有第一类型掺杂剂，其中第一保护环，第二保护环，第一掺杂区和第二掺杂区能够 可操作为第一可控硅整流器（SCR）以基本上释放静电放电（ESD）。

公开(公告)号：US20170256512A1

公开(公告)日：2017-09-07

申请号：US15601801

申请日：2017-05-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Wei Tu ,  Yian-Liang Kuo ,  Tsung-Fu Tsai ,  Ru-Ying Huang ,  Ming-Song Sheu ,  Hsien-Wei Chen

IPC分类号： H01L23/00 ,  H01L23/31

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0555 ,  H01L2224/05552 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/01023 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012

摘要： Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

公开(公告)号：US09748361B2

公开(公告)日：2017-08-29

申请号：US14312851

申请日：2014-06-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yu-Chang Jong ,  Chun-Chien Tsai

IPC分类号： H01L29/02 ,  H01L29/66 ,  H01L27/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L27/0251 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7835

摘要： An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated circuit further includes a second guard ring disposed around the first guard ring. The integrated circuit further includes a first doped region disposed adjacent to the first guard ring, the first doped region having a first dopant type. The integrated circuit further includes a second doped region disposed adjacent to the second guard ring, the second doped region having a second dopant type.

公开(公告)号：US20160005704A1

公开(公告)日：2016-01-07

申请号：US14853006

申请日：2015-09-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Wei Tu ,  Yian-Liang Kuo ,  Tsung-Fu Tsai ,  Ru-Ying Huang ,  Ming-Song Sheu ,  Hsien-Wei Chen

IPC分类号： H01L23/00 ,  H01L23/31

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0555 ,  H01L2224/05552 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/01023 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012

摘要： Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

公开(公告)号：US08551835B2

公开(公告)日：2013-10-08

申请号：US13769650

申请日：2013-02-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yao-Wu Feng

IPC分类号： H01L21/8249

CPC分类号： H01L29/66681 ,  H01L21/22 ,  H01L21/265 ,  H01L27/0259 ,  H01L29/0692 ,  H01L29/0839 ,  H01L29/0847 ,  H01L29/417 ,  H01L29/41758 ,  H01L29/66393 ,  H01L29/66659 ,  H01L29/7436 ,  H01L29/7835

摘要： Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well.

摘要翻译： 本发明的实施例涉及用于形成ESD装置的静电放电（ESD）装置和方法。 一个实施例是ESD保护装置，其包括：良好地布置在衬底中，n阱设置在衬底中;高压n阱（HVNW），其设置在衬底中的p阱和n阱之间;源极n +区域设置在 p阱以及设置在n阱中的多个漏极n +区域。

公开(公告)号：US10756079B2

公开(公告)日：2020-08-25

申请号：US15670649

申请日：2017-08-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yu-Chang Jong ,  Chun-Chien Tsai

IPC分类号： H01L29/02 ,  H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

摘要： A method for forming an integrated circuit includes forming a first guard ring around at least one transistor over a substrate. The method further includes forming a second guard ring around the first guard ring. The method further includes forming a first doped region adjacent to the first guard ring, the first doped region having a first dopant type. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having a second dopant type.

公开(公告)号：US10269750B2

公开(公告)日：2019-04-23

申请号：US15601801

申请日：2017-05-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Wei Tu ,  Yian-Liang Kuo ,  Tsung-Fu Tsai ,  Ru-Ying Huang ,  Ming-Song Sheu ,  Hsien-Wei Chen

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/525

摘要： Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

公开(公告)号：US09659890B2

公开(公告)日：2017-05-23

申请号：US14853006

申请日：2015-09-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Wei Tu ,  Yian-Liang Kuo ,  Tsung-Fu Tsai ,  Ru-Ying Huang ,  Ming-Song Sheu ,  Hsien-Wei Chen

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/525

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0555 ,  H01L2224/05552 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/01023 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012

摘要： Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

公开(公告)号：US09620414B2

公开(公告)日：2017-04-11

申请号：US14745595

申请日：2015-06-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Fu Tsai ,  Yian-Liang Kuo ,  Ming-Song Sheu ,  Yu-Ling Tsai ,  Chen-Shien Chen ,  Han-Ping Pu

IPC分类号： H01L23/29 ,  H01L21/78 ,  H01L21/56 ,  H01L23/00 ,  H01L21/02

CPC分类号： H01L21/78 ,  H01L21/02013 ,  H01L21/02016 ,  H01L21/563 ,  H01L23/295 ,  H01L23/562 ,  H01L24/32 ,  H01L24/743 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81009 ,  H01L2224/81191 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2924/10156 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2924/10155 ,  H01L2924/00

摘要： A die has a first surface, a second surface opposite the first surface, and sidewalls includes a first portion and a second portion, wherein the first portion is closer to the first surface than the second portion. A fillet contacts the first portion of sidewalls of the die and encircles the die. A work piece is bonded to the die through solder bumps, with the second surface facing the work piece. A first underfill is filled a gap between the die and the work piece, wherein the first underfill contacts the fillet, and wherein the first underfill and the fillet are formed of different materials.