公开(公告)号：US5815440A

公开(公告)日：1998-09-29

申请号：US822036

申请日：1997-03-24

申请人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita ,  Shouichi Kawamura

发明人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita ,  Shouichi Kawamura

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C29/00 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/80 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C2029/5004 ,  G11C29/88

摘要： A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2.sup.n word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

摘要翻译： 半导体存储器件具有2n字线，多个位线，设置在字线和位线的每个交叉处的多个非易失性存储器单元，写入电路用于将数据写入位于所选择的交叉点的存储器单元 字线和位线中的一个以及用于从存储器单元读出数据的读出放大器。 此外，半导体存储装置包括：第一单元，用于同时选择2n个字线中的2m（n> m）个字线的块;以及第二单元，用于不选择2k（m> k）个字线的块， 2m字线。 第二单元不选择2k个字线的块，并且当2m个字线中的任何2k个字线中的任一个有缺陷时，选择在2n个字线之外准备的2k个字线的块。 因此，有效地使用冗余字线，写入和验证操作是稳定的，从而提高半导体存储器件的产量和性能。

公开(公告)号：US06611464B2

公开(公告)日：2003-08-26

申请号：US10265233

申请日：2002-10-07

申请人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita ,  Shouichi Kawamura

发明人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita ,  Shouichi Kawamura

IPC分类号： G11C1604

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

公开(公告)号：US5452251A

公开(公告)日：1995-09-19

申请号：US79738

申请日：1993-06-22

申请人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

发明人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C29/00 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C11/40

CPC分类号： G11C29/80 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C2029/5004 ,  G11C29/88

摘要： A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2.sup.n word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

摘要翻译： 半导体存储器件具有2n字线，多个位线，设置在字线和位线的每个交叉处的多个非易失性存储器单元，写入电路用于将数据写入位于所选择的交叉点的存储器单元 字线和位线中的一个以及用于从存储器单元读出数据的读出放大器。 此外，半导体存储装置包括：第一单元，用于同时选择2n个字线中的2m（n> m）个字线的块;以及第二单元，用于不选择2k（m> k）个字线的块， 2m字线。 第二单元不选择2k个字线的块，并且当2m个字线中的任何2k个字线中的任一个有缺陷时，选择在2n个字线之外准备的2k个字线的块。 因此，有效地使用冗余字线，写入和验证操作是稳定的，从而提高半导体存储器件的产量和性能。

公开(公告)号：US06563738B2

公开(公告)日：2003-05-13

申请号：US10150017

申请日：2002-05-20

申请人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

发明人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

IPC分类号： G11C1604

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

公开(公告)号：US5666314A

公开(公告)日：1997-09-09

申请号：US432723

申请日：1995-06-06

申请人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

发明人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C29/00 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/80 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C2029/5004 ,  G11C29/88

摘要： A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2" word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

摘要翻译： 半导体存储器件具有2n字线，多个位线，设置在字线和位线的每个交叉处的多个非易失性存储器单元，写入电路用于将数据写入位于所选择的交叉点的存储器单元 字线和位线中的一个以及用于从存储器单元读出数据的读出放大器。 此外，半导体存储装置包括：第一单元，用于同时选择2n个字线中的2m（n> m）个字线的块;以及第二单元，用于不选择2k（m> k）个字线的块， 2m字线。 第二单元不选择2k个字线的块，并且当2m个字线中的任何2k个字线中的任何一个有缺陷时，选择2K字线以外准备的2k个字线的块。 因此，有效地使用冗余字线，写入和验证操作是稳定的，从而提高半导体存储器件的产量和性能。

公开(公告)号：US5770963A

公开(公告)日：1998-06-23

申请号：US436699

申请日：1995-05-08

申请人： Takao Akaogi ,  Hiromi Kawashima ,  Tetsuji Takeguchi ,  Ryoji Hagiwara ,  Yasushi Kasa ,  Kiyoshi Itano ,  Yasushige Ogawa ,  Shouichi Kawamura

发明人： Takao Akaogi ,  Hiromi Kawashima ,  Tetsuji Takeguchi ,  Ryoji Hagiwara ,  Yasushi Kasa ,  Kiyoshi Itano ,  Yasushige Ogawa ,  Shouichi Kawamura

IPC分类号： G05F3/20 ,  G11C5/14 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C29/00 ,  H03K3/356 ,  H03K19/0185 ,  H03K19/21 ,  H03K5/08

CPC分类号： G11C29/82 ,  G05F3/205 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C5/145 ,  H03K19/018521 ,  H03K19/215 ,  H03K3/356147 ,  H03K3/356165

摘要： A flash memory performs channel erasing or source erasing by applying a negative voltage to a control gate. The device includes a voltage restriction device which restricts the negative voltage to be applied to the control gate so that the negative voltage will be a constant value relative to the voltage of the channel or source. Alternatively, two voltage restricting devices restrict the negative voltage applied to the control gate and the voltage to be applied to the source so that the voltages will be a constant value relative to a common reference voltage.

摘要翻译： 闪存通过向控制栅极施加负电压来执行信道擦除或源擦除。 该装置包括限制施加到控制栅极的负电压的电压限制装置，使得负电压相对于通道或源的电压将是恒定值。 或者，两个电压限制装置限制施加到控制栅极的负电压和施加到源极的电压，使得电压相对于公共参考电压将是恒定值。

公开(公告)号：US5592419A

公开(公告)日：1997-01-07

申请号：US441598

申请日：1995-05-15

申请人： Takao Akaogi ,  Hiromi Kawashima ,  Tetsuji Takeguchi ,  Ryoji Hagiwara ,  Yasushi Kasa ,  Kiyoshi Itano ,  Yasushige Ogawa ,  Shouichi Kawamura

发明人： Takao Akaogi ,  Hiromi Kawashima ,  Tetsuji Takeguchi ,  Ryoji Hagiwara ,  Yasushi Kasa ,  Kiyoshi Itano ,  Yasushige Ogawa ,  Shouichi Kawamura

IPC分类号： G05F3/20 ,  G11C5/14 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C29/00 ,  H03K3/356 ,  H03K19/0185 ,  H03K19/21

CPC分类号： G11C29/82 ,  G05F3/205 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C5/145 ,  H03K19/018521 ,  H03K19/215 ,  H03K3/356147 ,  H03K3/356165

摘要： The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.

公开(公告)号：US5608670A

公开(公告)日：1997-03-04

申请号：US436721

申请日：1995-05-08

申请人： Takao Akaogi ,  Hiromi Kawashima ,  Tetsuji Takeguchi ,  Ryoji Hagiwara ,  Yasushi Kasa ,  Kiyoshi Itano ,  Yasushige Ogawa ,  Shouichi Kawamura

发明人： Takao Akaogi ,  Hiromi Kawashima ,  Tetsuji Takeguchi ,  Ryoji Hagiwara ,  Yasushi Kasa ,  Kiyoshi Itano ,  Yasushige Ogawa ,  Shouichi Kawamura

IPC分类号： G05F3/20 ,  G11C5/14 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C29/00 ,  H03K3/356 ,  H03K19/0185 ,  H03K19/21

CPC分类号： G11C29/82 ,  G05F3/205 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C5/145 ,  H03K19/018521 ,  H03K19/215 ,  H03K3/356147 ,  H03K3/356165

摘要： The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.

摘要翻译： 本发明涉及擦除闪存的改进。 本发明的目的是缩短擦除时间。 在预擦除写入期间，一次以多行单位选择字线或位线中的至少一个，并且数据被同时写入多个选择晶体管。

公开(公告)号：US5576637A

公开(公告)日：1996-11-19

申请号：US441460

申请日：1995-05-15

申请人： Takao Akaogi ,  Hiromi Kawashima ,  Tetsuji Takeguchi ,  Ryoji Hagiwara ,  Yasushi Kasa ,  Kiyoshi Itano ,  Yasushige Ogawa ,  Shouichi Kawamura

发明人： Takao Akaogi ,  Hiromi Kawashima ,  Tetsuji Takeguchi ,  Ryoji Hagiwara ,  Yasushi Kasa ,  Kiyoshi Itano ,  Yasushige Ogawa ,  Shouichi Kawamura

IPC分类号： G05F3/20 ,  G11C5/14 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C29/00 ,  H03K3/356 ,  H03K19/0185 ,  H03K19/21

CPC分类号： G11C29/82 ,  G05F3/205 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C5/145 ,  H03K19/018521 ,  H03K19/215 ,  H03K3/356147 ,  H03K3/356165

摘要： An exclusive OR circuit includes a first series circuit in which a source of a first pMIS transistor is connected to a positive-voltage power supply line. A drain of the first pMIS transistor is connected to a drain of a first nMIS transistor via a second nMIS transistor. The source of the first nMIS transistor is connected to a low-voltage power supply line via a fourth nMIS transistor. A second series circuit has a drain of a third nMIS transistor connected to a high-voltage power supply line via a second pMIS transistor. The source of the third nMIS transistor is connected to the source of a third pMIS transistor. The drain of the third pMIS transistor is connected to the low-voltage power supply line via a fourth pMIS transistor. The gates of the first and third nMIS transistors and the first and third pMIS transistors are connected to one another and provided with a first input. The gates of the second and fourth nMIS transistors and the second and fourth pMIS transistors are connected to one another and provided with a second input. The sources of the second and third nMIS transistors are connected to each other and provide the exclusive OR of the first and second inputs.

摘要翻译： 异或电路包括第一串联电路，其中第一pMIS晶体管的源极连接到正电压电源线。 第一pMIS晶体管的漏极经由第二nMIS晶体管连接到第一nMIS晶体管的漏极。 第一nMIS晶体管的源极经由第四nMIS晶体管连接到低压电源线。 第二串联电路具有通过第二pMIS晶体管连接到高压电源线的第三nMIS晶体管的漏极。 第三个nMIS晶体管的源极连接到第三个pMIS晶体管的源极。 第三个pMIS晶体管的漏极通过第四个pMIS晶体管连接到低压电源线。 第一和第三nMIS晶体管和第一和第三pMIS晶体管的栅极彼此连接并提供有第一输入。 第二和第四nMIS晶体管和第二和第四pMIS晶体管的栅极彼此连接并提供有第二输入。 第二和第三nMIS晶体管的源极彼此连接并提供第一和第二输入的异或。

公开(公告)号：US5631597A

公开(公告)日：1997-05-20

申请号：US445103

申请日：1995-05-19

申请人： Takao Akaogi ,  Hiromi Kawashima ,  Tetsuji Takeguchi ,  Ryoji Hagiwara ,  Yasushi Kasa ,  Kiyoshi Itano ,  Yasushige Ogawa ,  Shouichi Kawamura

发明人： Takao Akaogi ,  Hiromi Kawashima ,  Tetsuji Takeguchi ,  Ryoji Hagiwara ,  Yasushi Kasa ,  Kiyoshi Itano ,  Yasushige Ogawa ,  Shouichi Kawamura

IPC分类号： G05F3/20 ,  G11C5/14 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C29/00 ,  H03K3/356 ,  H03K19/0185 ,  H03K19/21 ,  G05F1/10

CPC分类号： G11C29/82 ,  G05F3/205 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C5/145 ,  H03K19/018521 ,  H03K19/215 ,  H03K3/356147 ,  H03K3/356165

摘要： A negative-voltage circuit for realizing a flash memory is installed independently and is applied selectively to word lines in response to signals sent from row decoders. Row decoders for specifying word lines need not be installed in the negative voltage circuit. The negative circuit can therefore be reduced in scale.

摘要翻译： 独立地安装用于实现闪速存储器的负电压电路，并响应于从行解码器发送的信号而选择性地对字线施加。 用于指定字线的行解码器不需要安装在负电压电路中。 因此，可以减小负电路的规模。