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公开(公告)号：US06862220B2
公开(公告)日：2005-03-01
申请号：US10886725
申请日：2004-07-09
IPC分类号： G11C16/04 , G06F15/78 , H01L21/28 , H01L21/82 , H01L21/8238 , H01L21/8247 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H03K19/173
CPC分类号： H01L29/792 , G11C16/0425 , G11C16/0466 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42324 , H01L29/42332 , H01L29/7885
摘要： A semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip is configured to achieve higher speed operation at a lower voltage. The semiconductor device includes a nonvolatile memory unit comprising a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined, according to logic constitution definition data to be loaded into storage cells thereof. A nonvolatile memory cell essentially has a split gate structure composed of a selecting MOS transistor and a memory MOS transistor and constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor. Because the selecting MOS transistor has a high Gm, a sufficiently great current for reading can be obtained.
摘要翻译： 包括安装在芯片上的非易失性存储单元和可变逻辑单元的半导体器件被配置为在较低电压下实现更高速度的操作。 半导体器件包括：非易失性存储器单元，其包括多个可重写非易失性存储器单元，以及根据要加载到其存储单元中的逻辑构造定义数据确定其逻辑功能的可变逻辑单元。 非易失性存储单元基本上具有由选择MOS晶体管和存储器MOS晶体管构成的分离栅极结构，并且被构造成使得选择MOS晶体管的栅极的介电耐受电压低于存储器MOS晶体管或栅极绝缘 选择MOS晶体管的层比耐高压MOS晶体管薄。 由于选择MOS晶体管具有高Gm，因此可以获得足够大的读取电流。
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公开(公告)号：US06785165B2
公开(公告)日：2004-08-31
申请号：US10309238
申请日：2002-12-04
IPC分类号： G11C1604
CPC分类号： H01L29/792 , G11C16/0425 , G11C16/0466 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42324 , H01L29/42332 , H01L29/7885
摘要： A semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip is configured to achieve higher speed operation at a lower voltage. The semiconductor device includes a nonvolatile memory unit comprising a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined, according to logic constitution definition data to be loaded into storage cells thereof. A nonvolatile memory cell essentially has a split gate structure composed of a selecting MOS transistor and a memory MOS transistor and constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor. Because the selecting MOS transistor has a high Gm, a sufficiently great current for reading can be obtained.
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3.发明申请Semiconductor device with a non-erasable memory and/or a nonvolatile memory 失效具有不可擦除存储器和/或非易失性存储器的半导体器件公开(公告)号：US20070159871A1
公开(公告)日：2007-07-12
申请号：US11715918
申请日：2007-03-09
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3454 , G11C2013/0092 , G11C2213/82
摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.
摘要翻译： 一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。 每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。 流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。 此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。 根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。
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公开(公告)号：US07206216B2
公开(公告)日：2007-04-17
申请号：US11057682
申请日：2005-02-15
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3454 , G11C2013/0092 , G11C2213/82
摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.
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公开(公告)号：US20050185445A1
公开(公告)日：2005-08-25
申请号：US11057682
申请日：2005-02-15
IPC分类号： G11C13/00 , G06F13/00 , G11C11/00 , G11C16/02 , G11C16/10 , G11C16/26 , G11C16/34 , G11C19/08 , H01L27/10 , H01L27/105
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3454 , G11C2013/0092 , G11C2213/82
摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.
摘要翻译： 一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。 每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。 流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。 此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。 根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。
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6.发明授权Semiconductor device with a non-erasable memory and/or a nonvolatile memory 失效具有不可擦除存储器和/或非易失性存储器的半导体器件公开(公告)号：US07385838B2
公开(公告)日：2008-06-10
申请号：US11715918
申请日：2007-03-09
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3454 , G11C2013/0092 , G11C2213/82
摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.
摘要翻译： 一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。 每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。 流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。 此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。 根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。
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公开(公告)号：US07180793B2
公开(公告)日：2007-02-20
申请号：US11156538
申请日：2005-06-21
IPC分类号： G11C7/10
CPC分类号： G11C16/24 , G11C7/065 , G11C7/067 , G11C7/18 , G11C16/26 , G11C16/28 , G11C2207/002 , H01L27/0207 , H01L27/105 , H01L27/11526
摘要： A semiconductor non-volatile storage device of the present invention which lets a memory cell directly drive up to a local bit line, wherein the output of the local bit line is received by a gate electrode of a separately-provided signal amplifying transistor, and the signal amplifying transistor is used to drive a global bit line having a large load capacity. Since an amplifying transistor having a drive power higher than a memory cell drives the parasitic capacity of a global bit line, information stored in a memory cell can be read out at high speed. Therefore, the storage device is used for storing program codes for controlling microcomputers or the like to thereby enhance a system performance.
摘要翻译： 本发明的半导体非易失性存储装置，其使存储器单元直接驱动到本地位线，其中本地位线的输出由单独提供的信号放大晶体管的栅电极接收，并且 信号放大晶体管用于驱动具有大负载能力的全局位线。 由于具有高于存储单元的驱动功率的放大晶体管驱动全局位线的寄生电容，因此可以高速读出存储在存储单元中的信息。 因此，存储装置用于存储用于控制微型计算机等的程序代码，从而提高系统性能。
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公开(公告)号：US20050237805A1
公开(公告)日：2005-10-27
申请号：US11156538
申请日：2005-06-21
IPC分类号： G11C7/06 , G11C7/18 , G11C11/34 , G11C16/24 , G11C16/26 , G11C16/28 , H01L27/02 , H01L27/105
CPC分类号： G11C16/24 , G11C7/065 , G11C7/067 , G11C7/18 , G11C16/26 , G11C16/28 , G11C2207/002 , H01L27/0207 , H01L27/105 , H01L27/11526
摘要： A semiconductor non-volatile storage device of the present invention which lets a memory cell directly drive up to a local bit line, wherein the output of the local bit line is received by a gate electrode of a separately-provided signal amplifying transistor, and the signal amplifying transistor is used to drive a global bit line having a large load capacity. Since an amplifying transistor having a drive power higher than a memory cell drives the parasitic capacity of a global bit line, information stored in a memory cell can be read out at high speed. Therefore, the storage device is used for storing program codes for controlling microcomputers or the like to thereby enhance a system performance.
摘要翻译： 本发明的半导体非易失性存储装置，其使存储器单元直接驱动到本地位线，其中本地位线的输出由单独提供的信号放大晶体管的栅电极接收，并且 信号放大晶体管用于驱动具有大负载能力的全局位线。 由于具有高于存储单元的驱动功率的放大晶体管驱动全局位线的寄生电容，因此可以高速读出存储在存储单元中的信息。 因此，存储装置用于存储用于控制微型计算机等的程序代码，从而提高系统性能。
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公开(公告)号：US06944056B2
公开(公告)日：2005-09-13
申请号：US10473817
申请日：2001-04-02
IPC分类号： G11C7/06 , G11C7/18 , G11C11/34 , G11C16/24 , G11C16/26 , G11C16/28 , H01L27/02 , H01L27/105 , G11C11/401
CPC分类号： G11C16/24 , G11C7/065 , G11C7/067 , G11C7/18 , G11C16/26 , G11C16/28 , G11C2207/002 , H01L27/0207 , H01L27/105 , H01L27/11526
摘要： A semiconductor non-volatile storage device of the present invention which lets a memory cell directly drive up to a local bit line, wherein the output of the local bit line is received by a gate electrode of a separately-provided signal amplifying transistor, and the signal amplifying transistor is used to drive a global bit line having a large load capacity. Since an amplifying transistor having a drive power higher than a memory cell drives the parasitic capacity of a global bit line, information stored in a memory cell can be read out at high speed. Therefore, the storage device is used for storing program codes for controlling microcomputers or the like to thereby enhance a system performance.
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公开(公告)号：US08618523B2
公开(公告)日：2013-12-31
申请号：US12302740
申请日：2006-05-31
申请人： Norikatsu Takaura , Yuichi Matsui , Motoyasu Terao , Yoshihisa Fujisaki , Nozomu Matsuzaki , Kenzo Kurotsuchi , Takahiro Morikawa
发明人： Norikatsu Takaura , Yuichi Matsui , Motoyasu Terao , Yoshihisa Fujisaki , Nozomu Matsuzaki , Kenzo Kurotsuchi , Takahiro Morikawa
IPC分类号： H01L47/00
CPC分类号： G11C13/0004 , G11C8/08 , G11C13/0028 , G11C2213/79 , H01L27/2436 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.
摘要翻译： 在嵌入作为下电极的插头（43）的绝缘膜（41）上，由氧化钽构成的绝缘膜（51）的叠层图案，由Ge-Sb-Te制成的记录层（52） 引入铟的硫属化合物和由钨或钨合金制成的上电极膜（53），从而形成相变存储器。 通过将绝缘膜（51）插入在记录层（52）和插塞（43）之间，可以实现降低相变存储器的编程电流的效果和防止记录层（52）的剥离的效果。 此外，通过使用引入了铟的Ge-Sb-Te类硫族化物作为记录层（52），绝缘膜（51）和记录层（52）之间的功函数差增大，编程 可以减小相变存储器的电压。
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