公开(公告)号：US4115796A

公开(公告)日：1978-09-19

申请号：US784715

申请日：1977-04-05

申请人： Takeo Fujimoto ,  Yasuo Torimaru ,  Shin-ichi Ogawa ,  Shinya Yasue

发明人： Takeo Fujimoto ,  Yasuo Torimaru ,  Shin-ichi Ogawa ,  Shinya Yasue

IPC分类号： H01L27/088 ,  H01L27/092 ,  H01L27/04

CPC分类号： H01L27/088 ,  H01L27/0927

摘要： Formation of well-regions of a conductivity type opposite to that of a substrate is achieved in such a manner to determine a first threshold voltage level. Ion implantation is effected on desirably selected gates in the respective channels formed on the substrate and the well-regions. Two channels on the ion implanted substrate and on the well-region in which the ion implantation is not effected, are coupled to form a complementary-MOS transistor pair having a first threshold voltage level. The channels on the substrate in which the ion implantation is not effected and on the ion implanted well-region are coupled to form another complementary-MOS transistor pair having a second threshold voltage level.

摘要翻译： 以确定第一阈值电压电平的方式实现与基板的导电类型相反的导电类型的阱区的形成。 在形成在衬底和阱区上的相应沟道中的期望选择的栅极上实现离子注入。 离子注入基板上的两个通道和不影响离子注入的阱区被耦合以形成具有第一阈值电压电平的互补MOS晶体管对。 不影响离子注入的衬底上的通道和离子注入的阱区被耦合以形成具有第二阈值电压电平的另一个互补MOS晶体管对。

公开(公告)号：US5821783A

公开(公告)日：1998-10-13

申请号：US778695

申请日：1997-01-03

申请人： Yasuo Torimaru ,  Atsushi Semi ,  Kaneo Kawaishi

发明人： Yasuo Torimaru ,  Atsushi Semi ,  Kaneo Kawaishi

IPC分类号： H03K17/12 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/0948 ,  H03B1/00

CPC分类号： H03K19/00361 ,  H03K19/018521

摘要： A buffer circuit according to the present invention includes an input terminal for inputting an input signal, an inverter circuit for inverting the input signal and outputting the inverted input signal to an output terminal, wherein the inverter circuit has a plurality of PMOS transistors and a plurality of NMOS transistors; each of the plurality of PMOS transistors has a source connected to a power source, a drain connected to the output terminal, and a gate connected to the input terminal; each of the plurality of NMOS transistors has a source connected to a ground, a drain connected to the output terminal, and a gate connected to the input terminal; and the gate of at least one of the plurality of PMOS transistors and NMOS transistors is connected to the input terminal via a fuse element which can be selectively disconnected.

摘要翻译： 根据本发明的缓冲电路包括用于输入输入信号的输入端子，用于反相输入信号并将反相输入信号输出到输出端的反相器电路，其中反相器电路具有多个PMOS晶体管和多个PMOS晶体管 的NMOS晶体管; 多个PMOS晶体管中的每一个具有连接到电源的源极，连接到输出端子的漏极和连接到输入端子的栅极; 多个NMOS晶体管中的每一个具有连接到地的源极，连接到输出端子的漏极和连接到输入端子的栅极; 并且多个PMOS晶体管和NMOS晶体管中的至少一个的栅极经由可选择性地断开的熔丝元件连接到输入端。

公开(公告)号：US5146430A

公开(公告)日：1992-09-08

申请号：US615876

申请日：1990-11-20

申请人： Yasuo Torimaru ,  Kouji Inoue

发明人： Yasuo Torimaru ,  Kouji Inoue

IPC分类号： G11C11/403 ,  G11C7/10 ,  G11C11/406

CPC分类号： G11C11/406 ,  G11C7/10

摘要： A field memory self-refresh system includes a dynamic random access memory (RAM) having memory cells arranged in a matrix of rows and columns. A row decoder is designated so that the data stored in the memory cells of a row corresponding to the designated row decoder are read out. Subsequently, a row address for refreshing the memory cell array is automatically generated by a refresh address counter which is located in the dynamic RAM, whereby the memory cells on the row of the memory cell array are refreshed without any external refresh control unit. The refresh system includes a refresh RAS signal generating circuit responsive to the output of a column counter. A multiplexer selects the output of a refresh address counter, a plurality of times, between activation of successive rows in response to the refresh RAS signal. Accordingly, it is possible to perform a self-refresh operation in a shortened refresh period.

摘要翻译： 场存储器自刷新系统包括具有以行和列的矩阵排列的存储单元的动态随机存取存储器（RAM）。 指定行解码器，使得存储在与指定行解码器相对应的行的存储单元中的数据被读出。 随后，用于刷新存储单元阵列的行地址由位于动态RAM中的刷新地址计数器自动生成，从而刷新存储单元阵列的行上的存储单元，而无需任何外部刷新控制单元。 刷新系统包括响应于列计数器的输出的刷新RAS信号发生电路。 多路复用器在响应于刷新RAS信号的连续行的激活之间多次选择刷新地址计数器的输出。 因此，可以在缩短的刷新周期中进行自刷新操作。

公开(公告)号：US5077495A

公开(公告)日：1991-12-31

申请号：US481307

申请日：1990-02-16

申请人： Yasuo Torimaru ,  Katsumi Sawai

发明人： Yasuo Torimaru ,  Katsumi Sawai

IPC分类号： G11C11/413 ,  G11C8/10 ,  H01L27/10 ,  H03K19/00 ,  H03K19/0948 ,  H03M7/00

CPC分类号： H03K19/0013 ,  G11C8/10 ,  H03K19/0948

摘要： A row decoder for a semiconductor memory device is disclosed. The row decoder comprises: CMOS NAND circuits each having P-channel transistors and N-channel transistors; and CMOS NOR circuits which follow the NAND circuits and have P-channel transistors and one or more N-channel transistors. The ratio of the channel length to the channel width of the P-channel transistors of the NAND circuits is greater than that of the N-channel transistors of the NAND circuits. And, the ratio of the channel length to the channel width of the N-channel transistors of the NOR circuits is greater than that of the P-channel transistors of the NOR circuits.

摘要翻译： 公开了一种用于半导体存储器件的行解码器。 行解码器包括：具有P沟道晶体管和N沟道晶体管的CMOS NAND电路; 和跟随NAND电路并具有P沟道晶体管和一个或多个N沟道晶体管的CMOS NOR电路。 NAND电路的P沟道晶体管的沟道长度与沟道宽度的比值大于NAND电路的N沟道晶体管的沟道长度。 并且，NOR电路的N沟道晶体管的沟道长度与沟道宽度的比值大于NOR电路的P沟道晶体管的比率。

公开(公告)号：US4589029A

公开(公告)日：1986-05-13

申请号：US530468

申请日：1983-09-08

申请人： Yasuo Torimaru ,  Masahiro Yoshimura

发明人： Yasuo Torimaru ,  Masahiro Yoshimura

IPC分类号： H04N5/66 ,  G02F1/133 ,  G06T3/40 ,  G09F9/30 ,  H04N5/225 ,  H04N5/232 ,  H04N5/30

CPC分类号： H04N5/23293 ,  G06T3/40

摘要： An electronic viewfinder comprises a plurality of picture elements which form a matrix image display device. A drive circuit is connected to the display device to cause the electronic viewfinder to selectively display a portion of the image, corresponding to the video signal being received by the drive circuit, at an increased magnification. The drive circuit includes frequency divider circuits for providing shift clock pulse signals at frequencies corresponding to the available rates of magnification of the image portion. The drive circuit further includes delay circuits for delaying synchronizing signals to select the portion of the image which is to be displayed. The electronic viewfinder having this drive circuit, is capable of providing increased resolution for a portion of an image by enlarging the image, while allowing the electronic viewfinder to be formed by a relatively small number of picture elements, so that the electronic viewfinder may be miniaturized and manufactured at a reduced cost.

摘要翻译： 电子取景器包括形成矩阵图像显示装置的多个图像元素。 驱动电路连接到显示装置，使得电子取景器以增加的放大率选择性地显示对应于由驱动电路接收的视频信号的图像的一部分。 驱动电路包括分频器电路，用于以对应于图像部分的可用放大率的频率提供移位时钟脉冲信号。 驱动电路还包括用于延迟同步信号以选择要显示的图像的部分的延迟电路。 具有该驱动电路的电子取景器能够通过放大图像来提供对图像的一部分的分辨率，同时允许电子取景器由相对较少数量的图像元素形成，使得电子取景器可以被小型化 并以降低成本制造。

公开(公告)号：US5347483A

公开(公告)日：1994-09-13

申请号：US27132

申请日：1993-03-05

申请人： Yasuo Torimaru

发明人： Yasuo Torimaru

IPC分类号： G11C15/00 ,  G11C15/04

CPC分类号： G11C15/046 ,  G11C15/00

摘要： A non-volatile memory cell is disclosed. The non-volatile memory cell includes first and second selecting transistors, first and second non-volatile memory transistors for storing data in a non-volatile manner, and first and second output transistors. A gate of the first selecting transistor and a gate of the second selecting transistor are connected to a word line. A drain of the first selecting transistor is connected to a first bit line, and a drain of the second selecting transistor is connected to a second bit line. A drain of the first non-volatile memory transistor is connected to a source of the first selecting transistor. A drain of the second non-volatile memory transistor is connected to a source of the second selecting transistor. A source of the first non-volatile memory transistor and a source of the second non-volatile memory transistor are connected to a source line. A gate of the first non-volatile memory transistor and a gate of the second non-volatile memory transistor are connected to a control gate line. A drain of the first output transistor and a drain of the second output transistor are connected to a first output line. A source of the first output transistor and a source of the second output transistor are connected to a second output line. A gate of the first output transistor is connected to a drain of the first non-volatile memory transistor. A gate of the second output transistor is connected to a drain of the second non-volatile memory transistor.

摘要翻译： 公开了一种非易失性存储单元。 非易失性存储单元包括第一和第二选择晶体管，用于以非易失性方式存储数据的第一和第二非易失性存储晶体管，以及第一和第二输出晶体管。 第一选择晶体管的栅极和第二选择晶体管的栅极连接到字线。 第一选择晶体管的漏极连接到第一位线，第二选择晶体管的漏极连接到第二位线。 第一非易失性存储晶体管的漏极连接到第一选择晶体管的源极。 第二非易失性存储晶体管的漏极连接到第二选择晶体管的源极。 第一非易失性存储晶体管的源极和第二非易失性存储晶体管的源极连接到源极线。 第一非易失性存储晶体管的栅极和第二非易失性存储晶体管的栅极连接到控制栅极线。 第一输出晶体管的漏极和第二输出晶体管的漏极连接到第一输出线。 第一输出晶体管的源极和第二输出晶体管的源极连接到第二输出线。 第一输出晶体管的栅极连接到第一非易失性存储晶体管的漏极。 第二输出晶体管的栅极连接到第二非易失性存储晶体管的漏极。

公开(公告)号：US5006725A

公开(公告)日：1991-04-09

申请号：US347711

申请日：1989-05-05

申请人： Masaru Nawaki ,  Yasuo Torimaru

发明人： Masaru Nawaki ,  Yasuo Torimaru

IPC分类号： H03K5/1532 ,  H03K5/00 ,  H03K5/13 ,  H03K5/1534

CPC分类号： H03K5/133 ,  H03K5/1534 ,  H03K2005/00195 ,  H03K2005/00293

摘要： A pulse generating unit including a delay unit for delaying an input signal of the pulse generating unit and a comparator unit for comparing an output signal of the delay unit with the above mentioned input signal, wherein the delay unit comprises one inverter for inverting the above mentioned input signal and for delaying the pulse fall time of the pulse fall edge of the inverted input signal, whereby the pulse generator generates an output pulse signal with a constant pulse duration even in the case where the pulse duration of the input pulse signal is shorter than the delay time of the delay unit.

摘要翻译： 一种脉冲发生单元，包括用于延迟脉冲发生单元的输入信号的延迟单元和用于将延迟单元的输出信号与上述输入信号进行比较的比较单元，其中延迟单元包括一个反相器，用于反转上述 并且用于延迟反相输入信号的脉冲下降沿的脉冲下降时间，由此即使在输入脉冲信号的脉冲持续时间短于脉冲信号的情况下，脉冲发生器也产生具有恒定脉冲持续时间的输出脉冲信号 延迟单元的延迟时间。

公开(公告)号：US5446688A

公开(公告)日：1995-08-29

申请号：US171715

申请日：1993-12-21

申请人： Yasuo Torimaru

发明人： Yasuo Torimaru

IPC分类号： G11C17/00 ,  G11C11/22 ,  G11C11/56 ,  G11C16/02 ,  G11C16/04 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11502 ,  G11C11/22 ,  G11C11/5657

摘要： A non-volatile semiconductor memory device, includes: a memory cell including an MOS transistor for reading, an MOS transistor for writing, and an MFS transistor provided with a gate having a ferroelectric film above a channel region, one of a drain and a source of the MFS transistor having a common electric potential; a bit line for writing, to which the gate of the MFS transistor is connected through the MOS transistor for writing, and to which multivalued data having at least three voltage levels or analog data is input; a bit line for reading, to which the other of the drain and the source of the MFS transistor is connected through the MOS transistor for reading, and from which multivalued data having at least three voltage levels or analog data is read; a word line for writing connected to a gate of the MOS transistor for writing; and a word line for reading connected to a gate of the MOS transistor for reading.

摘要翻译： 一种非易失性半导体存储器件，包括：包括用于读取的MOS晶体管，用于写入的MOS晶体管的存储单元，以及设置有在沟道区域上方具有铁电体膜的栅极的MFS晶体管，漏极和源极之一 具有公共电位的MFS晶体管; 用于写入的位线，MFS晶体管的栅极通过用于写入的MOS晶体管连接到其上，并且输入具有至少三个电压电平或模拟数据的多值数据; 用于读取的位线，MFS晶体管的漏极和源极中的另一个通过用于读取的MOS晶体管连接到其上，并从其读取具有至少三个电压电平或模拟数据的多值数据; 用于写入的字线连接到用于写入的MOS晶体管的栅极; 以及连接到用于读取的MOS晶体管的栅极的用于读取的字线。

公开(公告)号：US4972376A

公开(公告)日：1990-11-20

申请号：US268499

申请日：1988-11-08

申请人： Yasuo Torimaru ,  Kouji Inoue

发明人： Yasuo Torimaru ,  Kouji Inoue

IPC分类号： G11C11/403 ,  G11C7/10 ,  G11C11/406

CPC分类号： G11C11/406 ,  G11C7/10

摘要： In a dynamic Random Access Memory having memory cells arranged in a matrix shape, one of row decoders is designated so that the data stored in the memory cells of a row corresponding to the designated row decoder are read out. Subsequently, a row address for refreshing the memory cell array is automatically generated by a refresh address counter which is located in the dynamic Random Access Memory, thereby, the memory cells on the row of the memory cell array are refreshed without any external refresh control unit.

摘要翻译： 在具有以矩阵形状排列的存储单元的动态随机存取存储器中，指定行解码器之一，以便读出存储在与指定行解码器相对应的行的存储单元中的数据。 随后，用于刷新存储单元阵列的行地址由位于动态随机存取存储器中的刷新地址计数器自动产生，从而刷新存储单元阵列行上的存储单元，而无需任何外部刷新控制单元 。

公开(公告)号：US4947232A

公开(公告)日：1990-08-07

申请号：US277440

申请日：1988-11-28

申请人： Tsutomu Ashida ,  Kiyotoshi Nakagawa ,  Katsumasa Fujii ,  Yasuo Torimaru

发明人： Tsutomu Ashida ,  Kiyotoshi Nakagawa ,  Katsumasa Fujii ,  Yasuo Torimaru

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L29/405 ,  H01L29/7835

摘要： A metal oxide semiconductor device is featured by the provision of a covering element for covering a channel region of the semiconductor device there being interposed therebetween an insulating layer. The covering element is connected to at least one electrode selected from the drain electrode, the source electrode and the gate electrode. Therefore, the electrical level of the covering element is fixed.

摘要翻译： 金属氧化物半导体器件的特征在于，设置用于覆盖半导体器件的沟道区域的覆盖元件，其间插入有绝缘层。 覆盖元件连接到从漏电极，源电极和栅电极中选择的至少一个电极。 因此，覆盖元件的电平是固定的。