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    ESD protection structure using LDMOS diodes with thick copper interconnect
    3.
    发明授权
    ESD protection structure using LDMOS diodes with thick copper interconnect 失效
    使用具有厚铜互连的LDMOS二极管的ESD保护结构

    公开(公告)号：US5468984A

    公开(公告)日：1995-11-21

    申请号：US333407

    申请日：1994-11-02

    申请人： Taylor R. Efland ,  Dave Cotton ,  Dale J. Skelton

    发明人： Taylor R. Efland ,  Dave Cotton ,  Dale J. Skelton

    IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/866 ,  H01L27/085

    CPC分类号： H01L27/0255 ,  H01L23/4824 ,  H01L2924/0002 ,  Y10S438/983

    摘要： An interconnection structure and method for a multiple zener diode ESD protectoin circuit for power semiconductor devices. A plurality of lateral Zener diodes is formed. Each device is formed of a plurality of cathode and anode diffusion regions to be coupled together to form the cathode and anode of one or more Zener diodes. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form a bus. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive material, such as copper. The resulting Zener diodes are coupled together in an ESD structure using the second level busses and the thick copper third level busses. The ESD structure of the preferred embodiment has low overall resistance and fast time to breakdown and provides excellent protection for the circuits to be protected. Other devices, systems and methods are also disclosed.

    摘要翻译： 用于功率半导体器件的多齐纳二极管ESD保护电路的互连结构和方法。 形成多个侧向齐纳二极管。 每个器件由多个阴极和阳极扩散区域形成，以被耦合在一起以形成一个或多个齐纳二极管的阴极和阳极。 每个扩散区具有形成在其上并与其电接触的第一金属层条纹。 第二金属层导体形成在多个第一金属层条纹上，并且选择性地接触第一金属层条纹以形成总线。 然后在每个第二金属层母线上形成厚的第三金属层，或者物理地接触它或选择性地电接触它。 厚的第三级金属由诸如铜的高导电材料制成。 所得的齐纳二极管使用第二级总线和厚铜第三级总线以ESD结构耦合在一起。 优选实施例的ESD结构具有低的总体电阻和快速的击穿时间，并且为要保护的电路提供优异的保护。 还公开了其他装置，系统和方法。

    Ldmos transistor with thick copper interconnect
    4.
    发明授权
    Ldmos transistor with thick copper interconnect 失效
    Ldmos晶体管采用厚铜互连

    公开(公告)号：US6150722A

    公开(公告)日：2000-11-21

    申请号：US538873

    申请日：1995-10-04

    申请人： Taylor R. Efland ,  Dave Cotton ,  Dale J. Skelton

    发明人： Taylor R. Efland ,  Dave Cotton ,  Dale J. Skelton

    IPC分类号： H01L29/43 ,  H01L21/28 ,  H01L23/482 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L29/7835 ,  H01L23/4824 ,  H01L23/5286 ,  H01L29/41758 ,  H01L29/7801 ,  H01L23/53228 ,  H01L29/0696 ,  H01L29/41775 ,  H01L29/456 ,  H01L2924/0002

    摘要： A thick copper interconnection structure and method for an LDMOS transistor for power semiconductor devices. A large LDMOS transistor is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain. Gate regions are formed between the alternating source and drain diffusions. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form a source and a drain bus. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive copper layer. The thick third level metal bus substantially lowers the resistance of the LDMOS transistor and further eliminates current debiasing and early failure location problems experienced with LDMOS transistors of the prior art. Other devices and methods are described.

    摘要翻译： 一种用于功率半导体器件的LDMOS晶体管的厚铜互连结构和方法。 大的LDMOS晶体管由多个源极和漏极扩散区域形成以耦合在一起以形成源极和漏极。 栅极区域形成在交替的源极和漏极扩散之间。 每个扩散区具有形成在其上并与其电接触的第一金属层条纹。 第二金属层导体形成在多个第一金属层条纹上，并且选择性地接触第一金属层条纹以形成源极和漏极总线。 然后在每个第二金属层母线上形成厚的第三金属层，或者物理地接触它或选择性地电接触它。 厚三层金属由高导电铜层制成。 厚的第三级金属总线大大降低了LDMOS晶体管的电阻，并进一步消除了现有技术的LDMOS晶体管所经历的电流去差和早期故障定位问题。 描述其他设备和方法。

    Method for LDMOS transistor with thick copper interconnect
    5.
    发明授权
    Method for LDMOS transistor with thick copper interconnect 有权
    具有厚铜互连的LDMOS晶体管的方法

    公开(公告)号：US06372586B1

    公开(公告)日：2002-04-16

    申请号：US09566956

    申请日：2000-05-08

    申请人： Taylor R. Efland ,  Dave Cotton ,  Dale J. Skelton

    发明人： Taylor R. Efland ,  Dave Cotton ,  Dale J. Skelton

    IPC分类号： H01L21331

    CPC分类号： H01L29/7835 ,  H01L23/4824 ,  H01L23/53228 ,  H01L29/0696 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/7801 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A thick copper interconnection structure and method for an LDMOS transistor for power semiconductor devices. A large LDMOS transistor is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain. Gate regions are formed between the alternating source and drain diffusions. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form a source and a drain bus. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive copper layer. The thick third level metal bus substantially lowers the resistance of the LDMOS transistor and further eliminates current debiasing and early failure location problems experienced with LDMOS transistors of the prior art. Other devices and methods are described.

    摘要翻译： 用于功率半导体器件的LDMOS晶体管的厚铜互连结构和方法。 大的LDMOS晶体管由多个源极和漏极扩散区域形成以耦合在一起以形成源极和漏极。 栅极区域形成在交替的源极和漏极扩散之间。 每个扩散区具有形成在其上并与其电接触的第一金属层条纹。 第二金属层导体形成在多个第一金属层条纹上，并且选择性地接触第一金属层条纹以形成源极和漏极总线。 然后在每个第二金属层母线上形成厚的第三金属层，或者物理地接触它或选择性地电接触它。 厚三层金属由高导电铜层制成。 厚的第三级金属总线大大降低了LDMOS晶体管的电阻，并进一步消除了现有技术的LDMOS晶体管所经历的电流去差和早期故障定位问题。 描述其他设备和方法。

    Multiple transistor integrated circuit with thick copper interconnect
    6.
    发明授权
    Multiple transistor integrated circuit with thick copper interconnect 失效
    具有厚铜互连的多晶体管集成电路

    公开(公告)号：US5859456A

    公开(公告)日：1999-01-12

    申请号：US711138

    申请日：1996-09-09

    申请人： Taylor R. Efland ,  David Cotton ,  Dale J. Skelton

    发明人： Taylor R. Efland ,  David Cotton ,  Dale J. Skelton

    IPC分类号： H01L21/822 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/866 ,  H01L27/08

    CPC分类号： H01L29/7835 ,  H01L29/41758 ,  H01L29/7801

    摘要： An interconnection structure and method for a multiple transistor integrated circuit power device is disclosed. A power integrated circuit is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain of multiple LDMOS transistors. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form source and drain busses. Polysilicon gate busses are provided as well. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive material, such as copper. The resulting on resistance for the transistors on the integrated circuit is substantially reduced by the use of the thick third metal layer. Current debiasing and electromigration problems of the prior art are reduced or eliminated. A seven transistor integrated circuit formed from power transistors and incorporating the invention is described. Other devices, systems and methods are also disclosed.

    摘要翻译： 公开了一种用于多晶体管集成电路功率器件的互连结构和方法。 功率集成电路由多个源极和漏极扩散区域形成以耦合在一起以形成多个LDMOS晶体管的源极和漏极。 每个扩散区具有形成在其上并与其电接触的第一金属层条纹。 第二金属层导体形成在多个第一金属层条纹上，并且选择性地接触第一金属层条纹以形成源极和漏极总线。 也提供多晶硅栅母线总线。 然后在每个第二金属层母线上形成厚的第三金属层，或者物理地接触它或选择性地电接触它。 厚的第三级金属由诸如铜的高导电材料制成。 通过使用厚的第三金属层，集成电路上的晶体管的导通电阻大大降低。 减少或消除了现有技术的当前的去噪和电迁移问题。 描述了由功率晶体管形成并结合本发明的七晶体管集成电路。 还公开了其他装置，系统和方法。

    Method of making a multiple transistor integrated circuit with thick copper interconnect
    7.
    发明授权
    Method of making a multiple transistor integrated circuit with thick copper interconnect 失效
    制造具有厚铜互连的多晶体管集成电路的方法

    公开(公告)号：US5728594A

    公开(公告)日：1998-03-17

    申请号：US474621

    申请日：1995-06-07

    申请人： Taylor R. Efland ,  David Cotton ,  Dale J. Skelton

    发明人： Taylor R. Efland ,  David Cotton ,  Dale J. Skelton

    IPC分类号： H01L21/822 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/866 ,  H01L21/265

    CPC分类号： H01L29/7835 ,  H01L29/41758 ,  H01L29/7801

    摘要： An interconnection structure and method for a multiple transistor integrated circuit power device is disclosed. A power integrated circuit is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain of multiple LDMOS transistors. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form source and drain busses. Polysilicon gate busses are provided as well. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive material, such as copper. The resulting on resistance for the transistors on the integrated circuit is substantially reduced by the use of the thick third metal layer. Current debiasing and electromigration problems of the prior art are reduced or eliminated. A seven transistor integrated circuit formed from power transistors and incorporating the invention is described. Other devices, systems and methods are also disclosed.

    摘要翻译： 公开了一种用于多晶体管集成电路功率器件的互连结构和方法。 功率集成电路由多个源极和漏极扩散区域形成以耦合在一起以形成多个LDMOS晶体管的源极和漏极。 每个扩散区具有形成在其上并与其电接触的第一金属层条纹。 第二金属层导体形成在多个第一金属层条纹上，并且选择性地接触第一金属层条纹以形成源极和漏极总线。 也提供多晶硅栅母线总线。 然后在每个第二金属层母线上形成厚的第三金属层，或者物理地接触它或选择性地电接触它。 厚的第三级金属由诸如铜的高导电材料制成。 通过使用厚的第三金属层，集成电路上的晶体管的导通电阻大大降低。 减少或消除了现有技术的当前的去噪和电迁移问题。 描述了由功率晶体管形成并结合本发明的七晶体管集成电路。 还公开了其他装置，系统和方法。

    Sensing of current in a synchronous-buck power stage
    8.
    发明授权
    Sensing of current in a synchronous-buck power stage 有权
    在同步降压功率级中检测电流

    公开(公告)号：US6160388A

    公开(公告)日：2000-12-12

    申请号：US213681

    申请日：1998-12-17

    申请人： Dale J. Skelton ,  Chao-Chih Chiu ,  Taylor R. Efland

    发明人： Dale J. Skelton ,  Chao-Chih Chiu ,  Taylor R. Efland

    IPC分类号： H02M3/158 ,  G05F1/563

    CPC分类号： H02M3/1588 ,  H02M2001/0009 ,  Y02B70/1466

    摘要： A DC-DC converter that generates a sense signal representing a voltage drop across a low-side switch when the low-side switch is on. The sense signal is inverted and stored in a "hold" capacitor until the beginning of the next switching cycle. More specifically, an input node receives an input voltage V.sub.IN. A driver stage coupled to the input node and to a reference node chops V.sub.IN into a square wave under control of a PWM signal. The chopped V.sub.IN signal is coupled to an intermediate output node. An output stage coupled to the intermediate output node converts the chopped V.sub.IN signal to an output voltage V.sub.OUT to a load coupled to an output node. A sense unit coupled to sense a voltage on the intermediate output node generates a voltage signal indicating current flowing in the load.

    摘要翻译： DC-DC转换器，当低侧开关接通时，产生表示低侧开关上的电压降的感测信号。 感测信号被反相并存储在“保持”电容器中，直到下一个开关周期的开始。 更具体地，输入节点接收输入电压VIN。 耦合到输入节点和参考节点的驱动器级在PWM信号的控制下将VIN划分成方波。 斩波的VIN信号耦合到中间输出节点。 耦合到中间输出节点的输出级将斩波的VIN信号转换为耦合到输出节点的负载的输出电压VOUT。 耦合以感测中间输出节点上的电压的感测单元产生指示在负载中流动的电流的电压信号。

    Ripple regulator with improved initial accuracy and noise immunity
    9.
    发明授权
    Ripple regulator with improved initial accuracy and noise immunity 有权
    纹波调节器具有提高的初始精度和抗噪声能力

    公开(公告)号：US6147526A

    公开(公告)日：2000-11-14

    申请号：US213308

    申请日：1998-12-16

    申请人： Dale J. Skelton ,  Steven C. Jones ,  Taylor R. Efland ,  Lester L. Hodson

    发明人： Dale J. Skelton ,  Steven C. Jones ,  Taylor R. Efland ,  Lester L. Hodson

    IPC分类号： H02M3/156 ,  H02M3/158 ,  H03K7/08

    CPC分类号： H02M3/1563 ,  H02M3/1588 ,  Y02B70/1466

    摘要： A DC--DC converter having an input node receiving an input voltage V.sub.IN and generating an output voltage V.sub.OUT. A reference voltage generator provides a voltage V.sub.REF and a hysteresis voltage generator provides a voltage V.sub.HYST. A first comparator generates a signal determined from a difference between V.sub.REF and V.sub.OUT. A second comparator generates a signal determined from a difference between V.sub.OUT and V.sub.HYST. A latch is coupled to receive the outputs of the first and second comparators, and to generate an output. A driver circuit receives the latch output and generates a PWM signal used to switch the output stage. A double pulse suppression circuit masks off the latch inputs for a preselected time during the switching intervals fo the main power transistors to eliminate noise jitter.

    摘要翻译： 一种具有输入节点接收输入电压VIN并产生输出电压VOUT的DC-DC转换器。 参考电压发生器提供电压VREF，并且滞后电压发生器提供电压VHYST。 第一比较器产生从VREF和VOUT之间的差确定的信号。 第二比较器产生由VOUT和VHYST之间的差确定的信号。 锁存器被耦合以接收第一和第二比较器的输出，并且产生输出。 驱动器电路接收锁存器输出并产生用于切换输出级的PWM信号。 双脉冲抑制电路在主功率晶体管的切换间隔期间屏蔽锁存器输入预选的时间以消除噪声抖动。

    CMOS power device and method of construction and layout
    10.
    发明授权
    CMOS power device and method of construction and layout 失效
    CMOS功率器件及其构造和布局方法

    公开(公告)号：US5744843A

    公开(公告)日：1998-04-28

    申请号：US697693

    申请日：1996-08-28

    申请人： Taylor R. Efland ,  Dale J. Skelton

    发明人： Taylor R. Efland ,  Dale J. Skelton

    IPC分类号： H01L23/482 ,  H01L27/092 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/76 ,  H01L21/265

    CPC分类号： H01L29/1087 ,  H01L23/4824 ,  H01L27/0925 ,  H01L29/41758 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/3011

    摘要： CMOS power device (10) is provided. A tank region (62) is formed in a semiconductor substrate (60). A polysilicon gate layer (34) is disposed above the tank region (62) and defines a plurality of source and drain diffusion openings (38 and 36) having rounded inner corners (40). A plurality of backgate contact regions (42) are segmented and are formed in vacancies in a plurality of source regions (30). Multi-level metallization layers (64 and 66) are disposed above an active device region of the semiconductor substrate (60) and comprise: staggered source contacts (44) and vias (46) alternating along a center line where the source contacts (44) are located above and extend over the backgate contact regions (42), drain contacts (48) and vias (50) alternating along a center line, alternating and offset sets of gate contacts (52) and vias (54) alternating and offset where the sets are offset with respect to adjacent sets, source, drain and gate bussing (14, 16 and 20), and a center gate bus (22) located on a center line of the power device (10) coupled to the gate bussing (20). A plurality of source bond pads (18) and drain bond pads (29) are formed on opposite edges of the power device (10) and are coupled to the source bussing (14) and drain bussing (16), respectively. Thick upper level metallization (24) is disposed above the source bussing (14) and the drain bussing (16) and extends between associated bond pads (18 and 29).

    摘要翻译： 提供CMOS功率器件（10）。 在半导体衬底（60）中形成槽区（62）。 多晶硅栅极层（34）设置在槽区（62）的上方并且限定具有圆形内角（40）的多个源极和漏极扩散开口（38和36）。 多个后盖接触区域（42）被分段并形成在多个源区域（30）中的空位。 多层金属化层（64和66）设置在半导体衬底（60）的有源器件区域之上，并且包括：沿源极接触（44）的中心线交替的交错的源极接触（44）和通孔（46） 位于沿着中心线交替的后盖接触区域（42），漏极接触件（48）和通孔（50）之上并且延伸，交替和偏移组合的栅极触点（52）和通孔（54）交替和偏移，其中 源极，漏极和栅极总线（14,16和20）和位于功率器件（10）的中心线上的中心栅极总线（22）的耦合到栅极总线（20）的偏移 ）。 多个源极接合焊盘（18）和漏极接合焊盘（29）分别形成在功率器件（10）的相对边缘上并且分别耦合到源总线（14）和漏极总线（16）。 厚的上层金属化（24）设置在源总线（14）和漏极总线（16）上方并在相关联的接合焊盘（18和29）之间延伸。