公开(公告)号：US20160240509A1

公开(公告)日：2016-08-18

申请号：US15135364

申请日：2016-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heungkyu KWON ,  Kang Joon LEE ,  JaeWook YOO ,  Su-Chang LEE

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L23/13 ,  H01L23/16 ,  H01L23/18 ,  H01L23/3157 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13541 ,  H01L2224/13561 ,  H01L2224/13583 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13649 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/1367 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/13679 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/1401 ,  H01L2224/1403 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/1712 ,  H01L2224/17181 ,  H01L2224/175 ,  H01L2224/1751 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.

Abstract translation: 半导体封装包括包括中心部分和周边部分的第一基板，附接到第一基板的中心部分的至少一个第一中心连接部件和附接到第一基板的周边部分的至少一个第一周边连接部件。 第一中心连接构件包括第一支撑件和围绕第一支撑件的第一融合导电层。

公开(公告)号：US11749616B2

公开(公告)日：2023-09-05

申请号：US16042661

申请日：2018-07-23

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K Koduri

IPC: H01L23/488 ,  H01L23/00 ,  H01L23/552

CPC classification number: H01L23/552 ,  H01L23/488 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/95 ,  H01L2224/03318 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/0508 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/1191 ,  H01L2224/11312 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/1357 ,  H01L2224/1368 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13618 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/1403 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/17107 ,  H01L2224/32227 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2924/00014 ,  H01L2224/05186 ,  H01L2924/04953 ,  H01L2224/05186 ,  H01L2924/04941 ,  H01L2224/13111 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13113 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13012 ,  H01L2924/00012 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2224/13664 ,  H01L2924/00014 ,  H01L2224/13669 ,  H01L2924/00014 ,  H01L2224/13666 ,  H01L2924/00014 ,  H01L2224/13681 ,  H01L2924/00014 ,  H01L2224/13684 ,  H01L2924/00014 ,  H01L2224/13657 ,  H01L2924/00014 ,  H01L2224/13618 ,  H01L2924/00014 ,  H01L2224/1368 ,  H01L2924/00014

Abstract: A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

公开(公告)号：US20240162163A1

公开(公告)日：2024-05-16

申请号：US18461478

申请日：2023-09-05

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K Koduri

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/488

CPC classification number: H01L23/552 ,  H01L23/488 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/95 ,  H01L2224/03318 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/11312 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/1191 ,  H01L2224/13012 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13618 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/1403 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/17107 ,  H01L2224/32227 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83193

Abstract: A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

公开(公告)号：US20120299197A1

公开(公告)日：2012-11-29

申请号：US13478613

申请日：2012-05-23

Applicant: Heungkyu KWON ,  Kang Joon Lee ,  Jae Wook Yoo ,  Su-Chang Lee

Inventor： Heungkyu KWON ,  Kang Joon Lee ,  Jae Wook Yoo ,  Su-Chang Lee

IPC: H01L23/48

CPC classification number: H01L23/49811 ,  H01L23/13 ,  H01L23/16 ,  H01L23/18 ,  H01L23/3157 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13541 ,  H01L2224/13561 ,  H01L2224/13583 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13649 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/1367 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/13679 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/1401 ,  H01L2224/1403 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/1712 ,  H01L2224/17181 ,  H01L2224/175 ,  H01L2224/1751 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.

Abstract translation: 半导体封装包括包括中心部分和周边部分的第一基板，附接到第一基板的中心部分的至少一个第一中心连接部件和附接到第一基板的周边部分的至少一个第一周边连接部件。 第一中心连接构件包括第一支撑件和围绕第一支撑件的第一融合导电层。

公开(公告)号：US20190088608A1

公开(公告)日：2019-03-21

申请号：US15954254

申请日：2018-04-16

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Salvatore Frank Pavone ,  Christopher Daniel Manack

IPC: H01L23/00 ,  C25D5/12

CPC classification number: H01L24/11 ,  C25D3/30 ,  C25D3/38 ,  C25D3/56 ,  C25D3/562 ,  C25D3/60 ,  C25D5/022 ,  C25D5/10 ,  C25D5/12 ,  C25D5/18 ,  C25D5/505 ,  C25D7/00 ,  C25D7/123 ,  H01L21/288 ,  H01L23/49524 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05096 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13284 ,  H01L2224/13582 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13639 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1368 ,  H01L2224/13684 ,  H01L2224/13693 ,  H01L2224/16245 ,  H01L2224/16503 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01042 ,  H01L2924/01027 ,  H01L2924/01028

Abstract: A microelectronic device includes a reflow structure. The reflow structure has a copper-containing member and a solder member, and a barrier layer between them. The barrier layer has metal grains, with a diffusion barrier filler between the metal grains. The metal grains include at least a first metal and a second metal, each selected from nickel, cobalt, lanthanum, and cerium, with each having a concentration in the metal grains of at least 10 weight percent. The diffusion barrier filler includes at least a third metal, selected from tungsten and molybdenum. A combined concentration of tungsten and molybdenum in the diffusion barrier filler is higher than in the metal grains to provide a desired resistance to diffusion of copper. The barrier layer includes 2 weight percent to 15 weight percent of the combined concentration of tungsten, and molybdenum. A bump bond structure and a lead frame package are disclosed.

公开(公告)号：US5251806A

公开(公告)日：1993-10-12

申请号：US870647

申请日：1992-04-16

Applicant: Birendra N. Agarwala ,  Aziz M. Ahsan ,  Arthur Bross ,  Mark F. Chadurjian ,  Nicholas G. Koopman ,  Li-Chung Lee ,  Karl J. Puttlitz ,  Sudipta K. Ray ,  James G. Ryan ,  Joseph G. Schaefer ,  Kamalesh K. Srivastava ,  Paul A. Totta ,  Erick G. Walton ,  Adolf E. Wirsing

Inventor： Birendra N. Agarwala ,  Aziz M. Ahsan ,  Arthur Bross ,  Mark F. Chadurjian ,  Nicholas G. Koopman ,  Li-Chung Lee ,  Karl J. Puttlitz ,  Sudipta K. Ray ,  James G. Ryan ,  Joseph G. Schaefer ,  Kamalesh K. Srivastava ,  Paul A. Totta ,  Erick G. Walton ,  Adolf E. Wirsing

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L21/283

CPC classification number: H01L24/12 ,  H01L24/11 ,  H01L2224/11901 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/1367 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/13676 ,  H01L2224/13679 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L24/16 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15787 ,  H05K3/3431 ,  H05K3/3457

Abstract: The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.

Abstract translation: 本发明一般涉及新的互连及其制造方法，更具体地说，涉及一种细长的焊料互连及其制造方法。 在电子载体上，形成焊盘，在其上沉积焊料块并用金属层封盖，从而形成细长的焊料互连。 现在可以通过在已经被金属层覆盖的第一焊料块上形成第二焊料块来形成另外细长的焊料互连。 可以通过用金属覆盖层封盖前述焊料块和/或最后的焊料块来形成附加的细长焊料互连。 或者，封装层可以是形成在焊料块的侧壁上的侧壁间隔物的形式。

公开(公告)号：US5130779A

公开(公告)日：1992-07-14

申请号：US540256

申请日：1990-06-19

Applicant: Birendra N. Agarwala ,  Aziz M. Ahsan ,  Arthur Bross ,  Mark F. Chadurjian ,  Nicholas G. Koopman ,  Li-Chung Lee ,  Karl J. Puttlitz ,  Sudipta K. Ray ,  James G. Ryan ,  Joseph G. Schaefer ,  Kamalesh K. Srivastava ,  Paul A. Totta ,  Erick G. Walton ,  Adolf E. Wirsing

Inventor： Birendra N. Agarwala ,  Aziz M. Ahsan ,  Arthur Bross ,  Mark F. Chadurjian ,  Nicholas G. Koopman ,  Li-Chung Lee ,  Karl J. Puttlitz ,  Sudipta K. Ray ,  James G. Ryan ,  Joseph G. Schaefer ,  Kamalesh K. Srivastava ,  Paul A. Totta ,  Erick G. Walton ,  Adolf E. Wirsing

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/34

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/1367 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/13676 ,  H01L2224/13679 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15787 ,  H05K3/3431 ,  H05K3/3457

Abstract: The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.

Abstract translation: 本发明一般涉及新的互连及其制造方法，更具体地说，涉及一种细长的焊料互连及其制造方法。 在电子载体上，形成焊盘，在其上沉积焊料块并用金属层封盖，从而形成细长的焊料互连。 现在可以通过在已经被金属层覆盖的第一焊料块上形成第二焊料块来形成另外细长的焊料互连。 可以通过用金属覆盖层封盖前述焊料块和/或最后的焊料块来形成附加的细长焊料互连。 或者，封装层可以是形成在焊料块的侧壁上的侧壁间隔物的形式。

公开(公告)号：US09698088B2

公开(公告)日：2017-07-04

申请号：US15135364

申请日：2016-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heungkyu Kwon ,  Kang Joon Lee ,  JaeWook Yoo ,  Su-Chang Lee

IPC: H01L23/498 ,  H01L23/488 ,  H01L23/16 ,  H01L23/18 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/13

CPC classification number: H01L23/49811 ,  H01L23/13 ,  H01L23/16 ,  H01L23/18 ,  H01L23/3157 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13541 ,  H01L2224/13561 ,  H01L2224/13583 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13649 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/1367 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/13679 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/1401 ,  H01L2224/1403 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/1712 ,  H01L2224/17181 ,  H01L2224/175 ,  H01L2224/1751 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.

公开(公告)号：US20150371962A1

公开(公告)日：2015-12-24

申请号：US14734267

申请日：2015-06-09

Applicant: FUJITSU LIMITED

Inventor： TOSHIYA AKAMATSU

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/0361 ,  H01L2224/10145 ,  H01L2224/10175 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1161 ,  H01L2224/11825 ,  H01L2224/11826 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13624 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/13686 ,  H01L2224/16145 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81011 ,  H01L2224/81075 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/8192 ,  H01L2224/81951 ,  H01L2224/92127 ,  H01L2224/92225 ,  H01L2924/3512 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/053

Abstract: A terminal structure includes: a pillar containing a first metal material; and a cover layer covering an upper surface and a side surface of the pillar, the cover layer containing a second metal material into which a solder material diffuses more slowly than into the first metal material.And the terminal structure further includes a bonding layer over the cover layer, the bonding layer containing a metal material capable of solder bonding.

Abstract translation: 端子结构包括：包含第一金属材料的柱; 以及覆盖所述柱的上表面和侧表面的覆盖层，所述覆盖层包含第二金属材料，焊料材料比所述第一金属材料扩散更慢地扩散到所述第二金属材料中。 并且端子结构还包括覆盖层上的接合层，该接合层包含能够焊接的金属材料。

公开(公告)号：US08691691B2

公开(公告)日：2014-04-08

申请号：US13194214

申请日：2011-07-29

Applicant: Mukta G. Farooq ,  Troy L. Graves-Abe ,  William F. Landers ,  Kevin S. Petrarca ,  Richard P. Volant

Inventor： Mukta G. Farooq ,  Troy L. Graves-Abe ,  William F. Landers ,  Kevin S. Petrarca ,  Richard P. Volant

IPC: H01L21/44 ,  H01L21/311

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/10126 ,  H01L2224/11009 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11602 ,  H01L2224/11612 ,  H01L2224/11614 ,  H01L2224/11616 ,  H01L2224/13009 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/13583 ,  H01L2224/13584 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13679 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13683 ,  H01L2224/13684 ,  H01L2224/13687 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/053 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/00

Abstract: The present invention includes embodiments of a processing method, and resulting structure, for building a chip having a TSV pillar which can be used as an interconnecting structure. The process includes the deposition of a dual diffusion barrier between the TSV and the substrate the TSV is embedded within. The TSV is then exposed from the back side of the substrate so that at least a portion of the TSV protrudes from the substrate and can be used as a contact for connecting the chip to another surface. The resulting TSV is rigid, highly conductive, can be placed in a tightly pitched grid of contacts, and reduces effects of CTE mismatch.

Abstract translation: 本发明包括用于构建具有可用作互连结构的TSV柱的芯片的处理方法和结果的结构的实施例。 该过程包括在TSV和衬底之间沉积TSV和衬底之间的双重扩散阻挡层。 TSV然后从衬底的背面露出，使得TSV的至少一部分从衬底突出，并且可以用作用于将芯片连接到另一表面的接触件。 所产生的TSV是刚性的，高导电性的，可以放置在紧密连接的接触网格中，并减少CTE失配的影响。