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1.发明授权
公开(公告)号：US5719084A
公开(公告)日：1998-02-17
申请号：US564922
申请日：1995-11-29
申请人： Thomas G. Mallon , Chi-yi Kao , Wei-jen Hsia , Atsushi Shimoda
发明人： Thomas G. Mallon , Chi-yi Kao , Wei-jen Hsia , Atsushi Shimoda
IPC分类号： H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/768 , H01L21/469
CPC分类号： H01L21/31051 , H01L21/76819 , H01L21/7682
摘要： A method is provided for the controlled formation of voids in integrated circuit doped glass dielectric films. The film can be formed of borophosphosilica glass (BPSG) or other types of doped glass. The method involves the steps of providing a substrate on which conductors are formed, depositing a first layer of doped glass to a thickness in a predetermined ratio to the size of the space between conductors, reflowing the first doped glass layer, applying one or more additional doped glass layers to make up for any shortfall in desired total doped glass thickness, and performing a high temperature densification to smooth each additional layer. The method provides for increased integrated circuit speed by controlled formation of voids which have a low dielectric constant and therefore reduce capacitance between adjacent conductors. The method can be performed using existing doped glass deposition and reflow equipment.
摘要翻译： 提供了一种用于在集成电路掺杂的玻璃介电膜中控制形成空隙的方法。 该膜可由硼磷石玻璃（BPSG）或其他类型的掺杂玻璃形成。 该方法包括以下步骤：提供其上形成有导体的基板，将第一掺杂玻璃层以与导体之间的空间的尺寸预定比例的厚度沉积，回流第一掺杂玻璃层，施加一个或多个附加 掺杂的玻璃层以弥补所需的总掺杂玻璃厚度的任何不足，并且执行高温致密化以平滑每个附加层。 该方法通过控制形成具有低介电常数并因此降低相邻导体之间的电容的空隙来提供增加的集成电路速度。 该方法可以使用现有的掺杂玻璃沉积和回流设备进行。
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2.发明授权
公开(公告)号：US5278103A
公开(公告)日：1994-01-11
申请号：US23304
申请日：1993-02-26
申请人： Thomas G. Mallon , Chi-yi Kao , Wei-jen Hsia , Atsushi Shimoda
发明人： Thomas G. Mallon , Chi-yi Kao , Wei-jen Hsia , Atsushi Shimoda
IPC分类号： H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/768 , H01L21/473
CPC分类号： H01L21/31051 , H01L21/76819 , H01L21/7682
摘要： A method is provided for the controlled formation of voids in integrated circuit doped glass dielectric films. The film can be formed of borophosphosilica glass (BPSG) or other types of doped glass. The method involves the steps of providing a substrate on which conductors are formed, depositing a first layer of doped glass to a thickness in a predetermined ratio to the size of the space between conductors, reflowing the first doped glass layer, applying one or more additional doped glass layers to make up for any shortfall in desired total doped glass thickness, and performing a high temperature densification to smooth each additional layer. The method provides for increased integrated circuit speed by controlled formation of voids which have a low dielectric constant and therefore reduce capacitance between adjacent conductors. The method can be performed using existing doped glass deposition and reflow equipment.
摘要翻译： 提供了一种用于在集成电路掺杂的玻璃介电膜中控制形成空隙的方法。 该膜可由硼磷石玻璃（BPSG）或其他类型的掺杂玻璃形成。 该方法包括以下步骤：提供其上形成有导体的基板，将第一掺杂玻璃层以与导体之间的空间的尺寸预定比例的厚度沉积，回流第一掺杂玻璃层，施加一个或多个附加 掺杂的玻璃层以弥补所需的总掺杂玻璃厚度的任何不足，并且执行高温致密化以平滑每个附加层。 该方法通过控制形成具有低介电常数并因此降低相邻导体之间的电容的空隙来提供增加的集成电路速度。 该方法可以使用现有的掺杂玻璃沉积和回流设备进行。
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公开(公告)号：US5362353A
公开(公告)日：1994-11-08
申请号：US23305
申请日：1993-02-26
申请人： Thomas G. Mallon
发明人： Thomas G. Mallon
IPC分类号： H01J37/32 , H01L21/673 , C23F1/02
CPC分类号： H01L21/67386 , H01J37/32431 , Y10S156/917
摘要： An improved Faraday Cage is provided for use in reducing ion damage to semiconductor wafers during plasma etching. The improved Faraday Cage consists of a cylindrical metallic chamber having a cap at one or more ends. Semiconductor wafers are placed within the Cage and the Cage is suitably disposed within a plasma etcher. The caps substantially reduce the amount of harmful radiation which can enter the Cage and thereby ion damage to the wafers contained therein. The improved Faraday Cage can be conveniently integrated with a barrel-style plasma etcher by securing one of the Cage caps to the door of the plasma etcher such that opening and closing the door serves to disengage and engage one of the caps from the Cage.
摘要翻译： 提供了一种改进的法拉第笼，用于在等离子体蚀刻期间减少对半导体晶片的离子损伤。 改进的法拉第笼由一个或多个端部具有盖的圆柱形金属室组成。 将半导体晶片放置在笼中并且笼子适当地设置在等离子体蚀刻器内。 盖子基本上减少了可能进入笼子的有害辐射的量，从而对其中所含的晶片造成离子损伤。 改进的法拉第笼可以方便地与桶式等离子体蚀刻机集成，将其中一个笼盖盖住等离子体蚀刻器的门，使得打开和关闭门用于脱离并接合笼中的一个盖。
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公开(公告)号：US5628869A
公开(公告)日：1997-05-13
申请号：US239987
申请日：1994-05-09
申请人： Thomas G. Mallon
发明人： Thomas G. Mallon
IPC分类号： C23C16/509 , C23C16/52 , H01J37/32 , H01L21/316 , C23F1/02
CPC分类号： H01J37/32009 , C23C16/509 , C23C16/52 , H01J37/32541 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/31612 , Y10S428/901 , Y10T428/24802 , Y10T428/24917 , Y10T428/24926 , Y10T428/2495
摘要： A semiconductor integrated circuit is made by a process including the formation on a surface of a semiconductor integrated circuit processing wafer of a layer of material applied to the wafer by plasma enhanced chemical vapor deposition (PECVD). The layer of material may include plural sub-layers, the thicknesses of which are additive to result in the thickness of the layer of material itself. The sub-layers of material may have non-uniform thicknesses across a dimension of the processing wafer because of compromises in the process which are necessary to control various parameters of the material layer other than its thickness. These non-uniformities of thickness of the sub-layers may be controlled to offset one another so that the resulting layer of material has a substantially uniform thickness across the dimension of the processing wafer. A method, and apparatus for practicing the method, are set forth along with an explanation of how particular geometric factors of electrodes used in the PECVD process affect the resulting thickness non-uniformities. The thickness non-uniformities of the sub-layers may also be largely abated by use of the invention in a predictive-corrective fashion. A similar predictive-corrective method and resulting apparatus is set forth for gas plasma etching of an existing layer of material on a semiconductor integrated circuit processing wafer.
摘要翻译： 半导体集成电路通过包括通过等离子体增强化学气相沉积（PECVD）在晶片上施加的材料层的半导体集成电路处理晶片的表面上形成的工艺制成。 材料层可以包括多个子层，其厚度是相加的以导致材料层本身的厚度。 材料的子层在处理晶片的尺寸上可能具有不均匀的厚度，这是由于处理中的折衷是控制除了厚度之外的材料层的各种参数所必需的。 可以将这些子层厚度的不均匀性控制为彼此偏移，使得所得到的材料层在整个处理晶片的尺寸上具有基本均匀的厚度。 一起阐述了用于实施该方法的方法和装置，同时解释了在PECVD工艺中使用的电极的特定几何因子如何影响所产生的厚度非均匀性。 通过以预测的方式使用本发明，子层的厚度不均匀性也可大大减轻。 为了在半导体集成电路处理晶片上的现有材料层进行气体等离子体蚀刻，提出了类似的预测校正方法和所得到的装置。
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5.发明授权
公开(公告)号：US5516400A
公开(公告)日：1996-05-14
申请号：US239493
申请日：1994-05-09
IPC分类号： B24B1/00 , B24B37/22 , B24D13/14 , H01L21/304
CPC分类号： B24B37/22 , Y10S438/959 , Y10S451/921 , Y10T156/1026 , Y10T156/1034 , Y10T156/1052
摘要： A technique for mounting polishing pads to a platen in chemi-mechanical semiconductor wafer polishing apparatus is disclosed. A lower pad is mounted to the platen, and is trimmed to the size of the platen. An upper pad is mounted to the lower pad, and is sized so that an extreme outer edge portion of the upper pad extends beyond the trimmed outer edge of the lower pad. The outer edge portion of the upper pad is deformed downwardly, towards the lower pad. In this manner, polishing slurry is diverted from the pad-to-pad interface. Additionally, an integral annular lip can be formed on the front face of the upper pad, creating a reservoir for slurry to be retained on the face of the upper pad for enhancing residence time of the polishing slurry prior to the slurry washing over the face of the upper pad.
摘要翻译： 公开了一种在化学机械半导体晶片抛光装置中将抛光垫安装在台板上的技术。 下垫安装到压板上，并被修剪成压板的尺寸。 上垫被安装到下垫，并且其尺寸使得上垫的极端外边缘部分延伸超过下垫的修剪外边缘。 上垫的外边缘部分朝向下垫片向下变形。 以这种方式，抛光浆料从衬垫到衬垫界面转移。 此外，可以在上垫的前表面上形成一体的环形唇缘，从而产生用于浆料的储存器，以将其保留在上垫的表面上，以增强抛光浆料在淤浆洗涤之前的停留时间 上垫
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6.发明授权Method for adjusting the density of lines and contact openings across a substrate region for improving the chemical-mechanical polishing of a thin-film later disposed thereon 失效用于调整衬底区域上的线和接触开口的密度的方法，用于改进稍后设置在其上的薄膜的化学机械抛光
公开(公告)号：US6109775A
公开(公告)日：2000-08-29
申请号：US925021
申请日：1997-09-08
申请人： Prabhakar P. Tripathi , Keith Chao , Ratan K. Choudhury , Gauri C. Das , Nicholas K. Eib , Ashok K. Kapoor , Thomas G. Mallon
发明人： Prabhakar P. Tripathi , Keith Chao , Ratan K. Choudhury , Gauri C. Das , Nicholas K. Eib , Ashok K. Kapoor , Thomas G. Mallon
IPC分类号： H01L21/3105 , H01L21/768 , H01L23/522 , G06F17/00 , G06F17/50
CPC分类号： H01L21/76838 , H01L21/31053 , H01L21/76816 , H01L21/76819 , H01L23/522 , H01L2924/0002
摘要： Disclosed is the formation of additional lines, either dummy lines or active lines, in an electrically conductive pattern of lines to provide more uniform loading for either etching or chemical/mechanical polishing of a layer of electrically conductive material from which the pattern of lines is formed. Also disclosed is the use of additional or dummy vias to balance the loading during etching of the vias, as well as to provide stress relief for underlying metal in regions or areas having a low density of vias. Further disclosed is the use of a working grid on the integrated circuit structure to analyze the spacing of lines or vias for the above effects.
摘要翻译： 公开了在导电图案线中形成额外的线，虚拟线或有源线，以提供更均匀的负载，用于蚀刻或化学/机械抛光一层导电材料，从其形成线图案 。 还公开了使用额外的或虚拟的通孔来平衡通孔蚀刻期间的负载，以及为具有低密度通孔的区域或区域中的下面的金属提供应力释放。 还公开了在集成电路结构上使用工作网格以分析上述效应的线或通孔的间隔。
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7.发明授权Technique for improving within-wafer non-uniformity of material removal for performing CMP 失效用于改善晶片内不均匀性的技术，用于进行CMP的材料去除
公开(公告)号：US5722877A
公开(公告)日：1998-03-03
申请号：US729614
申请日：1996-10-11
摘要： A platen ring for use with a platen on a linear polisher, in which the platen ring is used to reduce fluctuation of the belt/pad assembly as it encounters the platen. The platen ring is disposed around the platen so that a fluctuation of the belt/pad assembly is dampened before the belt/pad assembly engages the platen. Reduction of the belt/pad fluctuation ensures a reduction in the within-wafer non-uniformity and provides for a more uniform polishing rate across the surface of the wafer.
摘要翻译： 与线性抛光机上的台板一起使用的压板环，其中压板环用于减小带/垫组件遇到压板时的波动。 压板环围绕压板设置，使得带/垫组件的波动在带/垫组件接合压板之前被润湿。 带/垫波动的减小确保了晶片内不均匀性的减少，并且提供跨越晶片表面的更均匀的抛光速率。
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公开(公告)号：US5667433A
公开(公告)日：1997-09-16
申请号：US481799
申请日：1995-06-07
申请人： Thomas G. Mallon
发明人： Thomas G. Mallon
IPC分类号： B24B53/007 , B24B53/017 , B24B5/00
CPC分类号： B24B53/017
摘要： A polishing pad conditioner has a grid with an abrasive surface for conditioning a polishing pad. Opposite the abrasive side of the grid, there is a back surface, having at least one key way, which extends at least partially into the back surface. A grid holder has a number of keys equal to the number of key ways in the back surface of the grid. The grid holder keys engage the grid key ways, thereby eliminating slippage between the grid and the grid holder. A mechanized arm is attached to the grid holder, and imparts a rotational and translational motion to the grid holder. A magnet may be used as an attachment means between the grid and the grid holder. The key ways of the grid and the keys of the grid holder may be arranged such that the grid holder can only receive the grid with the back surface of the grid facing the grid holder.
摘要翻译： 抛光垫调节器具有用于调节抛光垫的研磨表面的格栅。 与网格的研磨侧相对，具有后表面，其具有至少部分地延伸到后表面中的至少一个键方式。 网格保持器具有与网格背面中的键路数相等的多个键。 格栅支架键与格栅键相接合，从而消除格栅与格栅之间的滑动。 机械化的臂连接到栅格保持器，并向栅格保持器施加旋转和平移运动。 可以使用磁体作为栅格和栅格保持器之间的附接装置。 栅格和网格保持器的键的关键方式可以被布置成使得栅格保持器只能接收栅格的格栅，栅格的背面面向栅格保持器。
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9.发明授权Semiconductor integrated circuit processing wafer having a PECVD material layer of improved thickness uniformity 失效具有改进的厚度均匀性的PECVD材料层的半导体集成电路处理晶片
公开(公告)号：US5876838A
公开(公告)日：1999-03-02
申请号：US774948
申请日：1996-12-27
申请人： Thomas G. Mallon
发明人： Thomas G. Mallon
IPC分类号： C23C16/509 , C23C16/52 , H01J37/32 , H01L21/316 , B32B3/00
CPC分类号： H01J37/32009 , C23C16/509 , C23C16/52 , H01J37/32541 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/31612 , Y10S428/901 , Y10T428/24802 , Y10T428/24917 , Y10T428/24926 , Y10T428/2495
摘要： A semiconductor integrated circuit is made by a process including the formation on a surface of a semiconductor integrated circuit processing wafer of a layer of material applied to the wafer by plasma enhanced chemical vapor deposition (PECVD). The layer of material may include plural sub-layers, the thicknesses of which are additive to result in the thickness of the layer of material itself. The sub-layers of material may have non-uniform thicknesses across a dimension of the processing wafer because of compromises in the process which are necessary to control various parameters of the material layer other than its thickness. These non-uniformities of thickness of the sub-layers may be controlled to offset one another so that the resulting layer of material has a substantially uniform thickness across the dimension of the processing wafer. A method, and apparatus for practicing the method, are set forth along with an explanation of how particular geometric factors of electrodes used in the PECVD process affect the resulting thickness non-uniformities. The thickness non-uniformities of the sub-layers may also be largely abated by use of the invention in a predictive-corrective fashion. A similar predictive-corrective method and resulting apparatus is set forth for gas plasma etching of an existing layer of material on a semiconductor integrated circuit processing wafer.
摘要翻译： 半导体集成电路通过包括通过等离子体增强化学气相沉积（PECVD）在晶片上施加的材料层的半导体集成电路处理晶片的表面上形成的工艺制成。 材料层可以包括多个子层，其厚度是相加的以导致材料层本身的厚度。 材料的子层在处理晶片的尺寸上可能具有不均匀的厚度，这是由于处理中的折衷是控制除了厚度之外的材料层的各种参数所必需的。 可以将这些子层厚度的不均匀性控制为彼此偏移，使得所得到的材料层在整个处理晶片的尺寸上具有基本均匀的厚度。 一起阐述了用于实施该方法的方法和装置，同时解释了在PECVD工艺中使用的电极的特定几何因子如何影响所产生的厚度非均匀性。 通过以预测的方式使用本发明，子层的厚度不均匀性也可大大减轻。 为了在半导体集成电路处理晶片上的现有材料层进行气体等离子体蚀刻，提出了类似的预测校正方法和所得到的装置。
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10.发明授权Techniques for assembling polishing pads for chemi-mechanical polishing of silicon wafers 失效用于组装用于硅晶片化学机械抛光的抛光垫的技术
公开(公告)号：US5624304A
公开(公告)日：1997-04-29
申请号：US294570
申请日：1994-08-23
IPC分类号： B24B1/00 , B24B37/22 , B24D13/14 , H01L21/304 , B24B5/00
CPC分类号： B24B37/22 , Y10S438/959 , Y10S451/921 , Y10T156/1026 , Y10T156/1034 , Y10T156/1052
摘要： A technique for mounting polishing pads to a platen in chemi-mechanical semiconductor wafer polishing apparatus is disclosed. A lower pad is mounted to the platen, and is trimmed to the size of the platen. An upper pad is mounted to the lower pad, and is sized so that an extreme outer edge portion of the upper pad extends beyond the trimmed outer edge of the lower pad. The outer edge portion of the upper pad is deformed downwardly, towards the lower pad. In this manner, polishing slurry is diverted from the pad-to-pad interface. Additionally, an integral annular lip can be formed on the front face of the upper pad, creating a reservoir for slurry to be retained on the face of the upper pad for enhancing residence time of the polishing slurry prior to the slurry washing over the face of the upper pad.
摘要翻译： 公开了一种在化学机械半导体晶片抛光装置中将抛光垫安装在台板上的技术。 下垫安装到压板上，并被修剪成压板的尺寸。 上垫被安装到下垫，并且其尺寸使得上垫的极端外边缘部分延伸超过下垫的修剪外边缘。 上垫的外边缘部分朝向下垫片向下变形。 以这种方式，抛光浆料从衬垫到衬垫界面转移。 此外，可以在上垫的前表面上形成一体的环形唇缘，从而产生用于浆料的储存器，以将其保留在上垫的表面上，以增强抛光浆料在淤浆洗涤之前的停留时间 上垫
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