公开(公告)号：US20110156044A1

公开(公告)日：2011-06-30

申请号：US13027113

申请日：2011-02-14

申请人： Thomas H. Lee ,  Vivek Subramanian ,  James M. Cleeves ,  Andrew J. Walker ,  Christopher J. Petti ,  Igor G. Kouznetzov ,  Mark G. Johnson ,  Paul Michael Farmwald ,  Brad Herner

发明人： Thomas H. Lee ,  Vivek Subramanian ,  James M. Cleeves ,  Andrew J. Walker ,  Christopher J. Petti ,  Igor G. Kouznetzov ,  Mark G. Johnson ,  Paul Michael Farmwald ,  Brad Herner

IPC分类号： H01L29/786 ,  H01L29/78

CPC分类号： H01L27/11582 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5612 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0661 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7391 ,  H01L29/78642 ,  H01L29/7881 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/861 ,  H01L29/8616

摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

摘要翻译： 提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

公开(公告)号：US20120223380A1

公开(公告)日：2012-09-06

申请号：US13468731

申请日：2012-05-10

申请人： Thomas H. Lee ,  Vivek Subramanian ,  James M. Cleeves ,  Andrew J. Walker ,  Christopher J. Petti ,  Igor G. Kouznetzov ,  Mark G. Johnson ,  Paul Michael Farmwald ,  Brad Herner

发明人： Thomas H. Lee ,  Vivek Subramanian ,  James M. Cleeves ,  Andrew J. Walker ,  Christopher J. Petti ,  Igor G. Kouznetzov ,  Mark G. Johnson ,  Paul Michael Farmwald ,  Brad Herner

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L29/792

CPC分类号： H01L27/11582 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5612 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0661 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7391 ,  H01L29/78642 ,  H01L29/7881 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/861 ,  H01L29/8616

摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

摘要翻译： 提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

公开(公告)号：US06881994B2

公开(公告)日：2005-04-19

申请号：US09927648

申请日：2001-08-13

申请人： Thomas H. Lee ,  Vivek Subramanian ,  James M. Cleeves ,  Andrew J. Walker ,  Christopher J. Petti ,  Igor G. Kouznetzov ,  Mark G. Johnson ,  Paul Michael Farmwald ,  Brad Herner

发明人： Thomas H. Lee ,  Vivek Subramanian ,  James M. Cleeves ,  Andrew J. Walker ,  Christopher J. Petti ,  Igor G. Kouznetzov ,  Mark G. Johnson ,  Paul Michael Farmwald ,  Brad Herner

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/10 ,  H01L27/112 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L29/861 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L21/8242

CPC分类号： H01L27/11582 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5612 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0661 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7391 ,  H01L29/78642 ,  H01L29/7881 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/861 ,  H01L29/8616

摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

摘要翻译： 提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

公开(公告)号：US20090173985A1

公开(公告)日：2009-07-09

申请号：US12320351

申请日：2009-01-23

申请人： Thomas H. Lee ,  Vivek Subramanian ,  James M. Cleeves ,  Andrew J. Walker ,  Christopher J. Peti ,  Igor G. Kouznetzov ,  Mark G. Johnson ,  Paul Michael Farmwald

发明人： Thomas H. Lee ,  Vivek Subramanian ,  James M. Cleeves ,  Andrew J. Walker ,  Christopher J. Peti ,  Igor G. Kouznetzov ,  Mark G. Johnson ,  Paul Michael Farmwald

IPC分类号： H01L29/792 ,  H01L29/788

CPC分类号： H01L27/11582 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5612 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0661 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7391 ,  H01L29/78642 ,  H01L29/7881 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/861 ,  H01L29/8616

摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

摘要翻译： 提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

公开(公告)号：US08981457B2

公开(公告)日：2015-03-17

申请号：US13468731

申请日：2012-05-10

申请人： Thomas H. Lee ,  Vivek Subramanian ,  James M. Cleeves ,  Mark G. Johnson ,  Paul Michael Farmwald ,  Igor G. Kouznetzov

发明人： Thomas H. Lee ,  Vivek Subramanian ,  James M. Cleeves ,  Mark G. Johnson ,  Paul Michael Farmwald ,  Igor G. Kouznetzov

IPC分类号： H01L29/788 ,  H01L27/115 ,  G11C16/34 ,  H01L21/822 ,  H01L27/06 ,  H01L27/112 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L29/861 ,  H01L27/12

CPC分类号： H01L27/11582 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5612 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0661 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7391 ,  H01L29/78642 ,  H01L29/7881 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/861 ,  H01L29/8616

摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

公开(公告)号：US08503215B2

公开(公告)日：2013-08-06

申请号：US13526671

申请日：2012-06-19

申请人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

发明人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

IPC分类号： G11C11/36

CPC分类号： G11C17/06 ,  G11C11/5692 ,  G11C13/003 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/16

摘要： A memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. The steering element and state change element are disposed in a vertically-oriented pillar. Other aspects are also provided.

摘要翻译： 提供了一种存储单元，其包括转向元件和与该转向元件串联耦合的非易失性状态变化元件。 转向元件和状态改变元件设置在垂直定向的支柱中。 还提供其他方面。

公开(公告)号：US20120250396A1

公开(公告)日：2012-10-04

申请号：US13526671

申请日：2012-06-19

申请人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

发明人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

IPC分类号： G11C11/00 ,  H01L21/8239

CPC分类号： G11C17/06 ,  G11C11/5692 ,  G11C13/003 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/16

摘要： A memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. The steering element and state change element are disposed in a vertically-oriented pillar. Other aspects are also provided.

摘要翻译： 提供了一种存储单元，其包括转向元件和与该转向元件串联耦合的非易失性状态变化元件。 转向元件和状态改变元件设置在垂直定向的支柱中。 还提供其他方面。

公开(公告)号：US06483736B2

公开(公告)日：2002-11-19

申请号：US09939431

申请日：2001-08-24

申请人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

发明人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

IPC分类号： G11C1100

CPC分类号： G11C17/06 ,  G11C11/5692 ,  G11C13/003 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/16

摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

公开(公告)号：US6034882A

公开(公告)日：2000-03-07

申请号：US192883

申请日：1998-11-16

申请人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

发明人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

IPC分类号： H01L27/10 ,  G11C11/56 ,  G11C17/16 ,  H01L27/102 ,  G11C17/00

CPC分类号： H01L27/1021 ,  G11C11/5692 ,  G11C13/003 ,  G11C17/16 ,  G11C11/5678 ,  G11C2213/71 ,  G11C2213/76

摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

公开(公告)号：US06385074B1

公开(公告)日：2002-05-07

申请号：US09748816

申请日：2000-12-22

申请人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

发明人： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

IPC分类号： G11C1700

CPC分类号： H01L27/1021 ,  G11C11/5692 ,  G11C17/14 ,  G11C17/16 ,  G11C2213/71 ,  H01L27/0203 ,  H01L27/115

摘要： An integrated circuit device includes a three-dimensional memory array and array terminal circuitry for providing to selected memory cells of the array a write voltage different from a read voltage. Neither voltage is necessarily equal to a VDD power supply voltage supplied to the integrated circuit. The write voltage, particularly if greater than VDD, may be generated by an on-chip voltage generator, such as a charge pump, which may require an undesirably large amount of die area, particularly relative to a higher bit density three-dimensional memory array formed entirely in layers above a semiconductor substrate. In several preferred embodiments, the area directly beneath a memory array is advantageously utilized to layout at least some of the write voltage generator, thus locating the generator near the selected memory cells during a write operation.

摘要翻译： 集成电路器件包括三维存储器阵列和阵列端子电路，用于向阵列的选定存储单元提供不同于读取电压的写入电压。 两个电压都不一定等于提供给集成电路的VDD电源电压。 特别是如果大于VDD的写入电压可以由片上电压发生器（例如电荷泵）产生，其可能需要不期望的大量管芯面积，特别是相对于较高位密度的三维存储器阵列 完全以半导体衬底上的层形成。 在几个优选实施例中，存储器阵列正下方的区域有利地用于布置写入电压发生器中的至少一些，从而在写入操作期间将发生器定位在选定的存储器单元附近。