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公开(公告)号:US10529539B2
公开(公告)日:2020-01-07
申请号:US15290846
申请日:2016-10-11
发明人: Akira Koshiishi , Masaru Sugimoto , Kunihiko Hinata , Noriyuki Kobayashi , Chishio Koshimizu , Ryuji Ohtani , Kazuo Kibi , Masashi Saito , Naoki Matsumoto , Manabu Iwata , Daisuke Yano , Yohei Yamazawa , Hidetoshi Hanaoka , Toshihiro Hayami , Hiroki Yamazaki , Manabu Sato
IPC分类号: C23F1/00 , H01L21/306 , H01J37/32 , H01L21/3065
摘要: An apparatus includes an upper electrode and a lower electrode for supporting a wafer disposed opposite each other within a process chamber. A first RF power supply configured to apply a first RF power having a relatively higher frequency, and a second RF power supply configured to apply a second RF power having a relatively lower frequency is connected to the lower electrode. A variable DC power supply is connected to the upper electrode. A process gas is supplied into the process chamber to generate plasma of the process gas so as to perform plasma etching.
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公开(公告)号:US20140326409A1
公开(公告)日:2014-11-06
申请号:US14331690
申请日:2014-07-15
发明人: Akira KOSHIISHI , Masaru Sugimoto , Kunihiko Hinata , Noriyuki Kobayashi , Chishio Koshimizu , Ryuji Ohtani , Kazuo Kibi , Masashi Saito , Naoki Matsumoto , Manabu Iwata , Daisuke Yano , Yohei Yamazawa
CPC分类号: H01J37/32091 , H01J37/32082 , H01J37/32174 , H01J37/32348 , H01J37/3244 , H01J37/32541 , H01J37/32568 , H01J37/32642 , H01J37/32706 , H01J37/32834 , H01J2237/3344 , H01L21/02126 , H01L21/02164 , H01L21/0217 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/67069
摘要: An apparatus includes an upper electrode and a lower electrode for supporting a wafer disposed opposite each other within a process chamber. A first RF power supply configured to apply a first RF power having a relatively higher frequency is connected to the upper electrode. A second RF power supply configured to apply a second RF power having a relatively lower frequency is connected to the lower electrode. A variable DC power supply is connected to the upper electrode. A process gas is supplied into the process chamber while any one of application voltage, application current, and application power from the variable DC power supply to the upper electrode is controlled, to generate plasma of the process gas so as to perform plasma etching.
摘要翻译: 一种装置包括用于支撑在处理室内相对设置的晶片的上电极和下电极。 被配置为施加具有相对较高频率的第一RF功率的第一RF电源连接到上电极。 配置为施加具有相对较低频率的第二RF功率的第二RF电源连接到下电极。 可变直流电源连接到上电极。 将处理气体供给到处理室中,同时控制从可变直流电源到上部电极的施加电压,施加电流和施加电力中的任何一个,以产生处理气体的等离子体,以进行等离子体蚀刻。
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公开(公告)号:US11282753B2
公开(公告)日:2022-03-22
申请号:US16963362
申请日:2019-01-21
发明人: Kazuo Kibi
IPC分类号: H01L21/8238 , H01L21/02 , H01L21/311 , H01L27/092 , H01L29/417
摘要: In a method for manufacturing a semiconductor device that comprises a semiconductor fin including a source region and a drain region, which configure a field effect transistor, and a fixed potential line provided in parallel to the semiconductor fin, the method comprises: a first step of preparing an intermediate body in which an insulating layer is provided on the source region (P-type conductive region), the drain region (N-type conductive region), and the fixed potential line; and a second step of simultaneously forming contact holes leading to the source region, the drain region, and the fixed potential line, in the insulating layer.
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公开(公告)号:US10854431B2
公开(公告)日:2020-12-01
申请号:US16708856
申请日:2019-12-10
发明人: Akira Koshiishi , Masaru Sugimoto , Kunihiko Hinata , Noriyuki Kobayashi , Chishio Koshimizu , Ryuji Ohtani , Kazuo Kibi , Masashi Saito , Naoki Matsumoto , Yoshinobu Ohya , Manabu Iwata , Daisuke Yano , Yohei Yamazawa , Hidetoshi Hanaoka , Toshihiro Hayami , Hiroki Yamazaki , Manabu Sato
摘要: A plasma processing method includes executing an etching process that includes supplying an etching gas into a process container in which a target substrate is supported on a second electrode serving as a lower electrode, and applying an RF power for plasma generation and an RF power for ion attraction to turn the etching gas into plasma and to subject the target substrate to etching. The etching process includes applying a negative DC voltage to a first electrode serving as an upper electrode during the etching to increase an absolute value of self-bias on the first electrode. The etching process includes releasing DC electron current generated by the negative DC voltage to ground through plasma and a conductive member disposed as a ring around the first electrode, by using a first state where the conductive member is connected to a ground potential portion.
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公开(公告)号:US12100616B2
公开(公告)日:2024-09-24
申请号:US17445436
申请日:2021-08-19
发明人: Kazuo Kibi , Shigetsugu Fujita , Kenji Suzuki , Mitsuhiro Okada
IPC分类号: H01L21/768 , H01L21/027
CPC分类号: H01L21/76805 , H01L21/0274 , H01L21/76877
摘要: A method of manufacturing a semiconductor device includes: planarizing a surface of a substrate having a conductive material embedded in a first hole so as to expose the conductive material embedded in the first hole, wherein the first hole is formed in a region which is on an insulating film laminated on the substrate and is surrounded by a spacer film; laminating a mask film on the surface of the substrate; forming a second hole in the mask film such that at least a portion of an upper surface of the conductive material embedded in the first hole is exposed; embedding the conductive material in the second hole; and removing the mask film.
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公开(公告)号:US11501998B2
公开(公告)日:2022-11-15
申请号:US16996914
申请日:2020-08-19
发明人: Kazuo Kibi , Akihiro Takahashi , Wataru Sakamoto
IPC分类号: H01L21/768 , H01L21/033 , H01L21/311 , H01L21/3213 , H01L27/11556 , H01L27/11582
摘要: There is formed, on a stack formed by alternately stacking an oxide film and a nitride film or an oxide film and a polysilicon film on a substrate, a hard mask in which two or more kinds of lines made of mutually different materials are arranged in order. Then, a photoresist is applied onto the hard mask. Furthermore, the photoresist is trimmed until one line is exposed from the end of the hard mask. Moreover, one line of the hard mask exposed beneath the photoresist is etched. Furthermore, a part of the stack exposed beneath the hard mask is etched. The etching of the photoresist, the hard mask, and the stack is repeated while changing etching conditions.
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公开(公告)号:US20160379805A1
公开(公告)日:2016-12-29
申请号:US15258607
申请日:2016-09-07
发明人: Akira KOSHIISHI , Masaru Sugimoto , Kunihiko Hinata , Noriyuki Kobayashi , Chishio Koshimizu , Ryuji Ohtani , Kazuo Kibi , Masashi Saito , Naoki Matsumoto , Yoshinobu Ohya , Manabu Iwata , Daisuke Yano , Yohei Yamazawa , Hidetoshi Hanaoka , Toshihiro Hayami , Hiroki Yamazaki , Manabu Sato
CPC分类号: H01J37/32422 , H01J37/32018 , H01J37/32091 , H01J37/3244 , H01J37/32522 , H01J37/32834 , H01J2237/2001 , H01J2237/334 , H01J2237/3344 , H01L21/67069 , Y10S156/915
摘要: A plasma etching apparatus includes an upper electrode and a lower electrode, between which plasma of a process gas is generated to perform plasma etching on a wafer W. The apparatus further comprises a cooling ring disposed around the wafer, a correction ring disposed around the cooling ring, and a variable DC power supply directly connected to the correction ring, the DC voltage being preset to provide the correction ring with a negative bias, relative to ground potential, for attracting ions in the plasma and to increase temperature of the correction ring to compensate for a decrease in temperature of a space near the edge of the target substrate due to the cooling ring.
摘要翻译: 等离子体蚀刻装置包括上电极和下电极,在其间产生处理气体的等离子体以在晶片W上进行等离子体蚀刻。该装置还包括设置在晶片周围的冷却环,设置在冷却周围的校正环 环和直接连接到校正环的可变直流电源,所述直流电压被预设为向校正环提供相对于地电位的负偏压,用于吸引等离子体中的离子并将校正环的温度增加到 补偿由于冷却环导致的目标基板的边缘附近的空间的温度的降低。
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公开(公告)号:US20160358753A1
公开(公告)日:2016-12-08
申请号:US15238526
申请日:2016-08-16
发明人: Akira KOSHIISHI , Masaru Sugimoto , Kunihiko Hinata , Noriyuki Kobayashi , Chishio Koshimizu , Ryuji Ohtani , Kazuo Kibi , Masashi Saito , Naoki Matsumoto , Manabu Iwata , Daisuke Yano , Yohei Yamazawa
IPC分类号: H01J37/32 , H01L21/311 , H01L21/02 , H01L21/67
CPC分类号: H01J37/32091 , H01J37/32082 , H01J37/32174 , H01J37/32348 , H01J37/3244 , H01J37/32541 , H01J37/32568 , H01J37/32642 , H01J37/32706 , H01J37/32834 , H01J2237/3344 , H01L21/02126 , H01L21/02164 , H01L21/0217 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/67069
摘要: An apparatus includes an upper electrode and a lower electrode for supporting a wafer disposed opposite each other within a process chamber. A first RF power supply configured to apply a first RF power having a relatively higher frequency is connected to the upper electrode. A second RF power supply configured to apply a second RF power having a relatively lower frequency is connected to the lower electrode. A variable DC power supply is connected to the upper electrode. A process gas is supplied into the process chamber while any one of application voltage, application current, and application power from the variable DC power supply to the upper electrode is controlled, to generate plasma of the process gas so as to perform plasma etching.
摘要翻译: 一种装置包括用于支撑在处理室内相对设置的晶片的上电极和下电极。 被配置为施加具有相对较高频率的第一RF功率的第一RF电源连接到上电极。 配置为施加具有相对较低频率的第二RF功率的第二RF电源连接到下电极。 可变直流电源连接到上电极。 将处理气体供给到处理室中,同时控制来自可变直流电源到上部电极的施加电压,施加电流和施加电力中的任何一个,以产生处理气体的等离子体,以进行等离子体蚀刻。
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公开(公告)号:US10546727B2
公开(公告)日:2020-01-28
申请号:US15258607
申请日:2016-09-07
发明人: Akira Koshiishi , Masaru Sugimoto , Kunihiko Hinata , Noriyuki Kobayashi , Chishio Koshimizu , Ryuji Ohtani , Kazuo Kibi , Masashi Saito , Naoki Matsumoto , Yoshinobu Ohya , Manabu Iwata , Daisuke Yano , Yohei Yamazawa , Hidetoshi Hanaoka , Toshihiro Hayami , Hiroki Yamazaki , Manabu Sato
IPC分类号: C23F1/00 , H01L21/306 , H01J37/32 , H01L21/67
摘要: A plasma etching apparatus includes an upper electrode and a lower electrode, between which plasma of a process gas is generated to perform plasma etching on a wafer W. The apparatus further comprises a cooling ring disposed around the wafer, a correction ring disposed around the cooling ring, and a variable DC power supply directly connected to the correction ring, the DC voltage being preset to provide the correction ring with a negative bias, relative to ground potential, for attracting ions in the plasma and to increase temperature of the correction ring to compensate for a decrease in temperature of a space near the edge of the target substrate due to the cooling ring.
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公开(公告)号:US09490105B2
公开(公告)日:2016-11-08
申请号:US14070190
申请日:2013-11-01
发明人: Akira Koshiishi , Masaru Sugimoto , Kunihiko Hinata , Noriyuki Kobayashi , Chishio Koshimizu , Ryuji Ohtani , Kazuo Kibi , Masashi Saito , Naoki Matsumoto , Yoshinobu Ohya , Manabu Iwata , Daisuke Yano , Yohei Yamazawa , Hidetoshi Hanaoka , Toshihiro Hayami , Hiroki Yamazaki , Manabu Sato
IPC分类号: C23F1/00 , C23C16/00 , H01L21/306 , H01J37/32
CPC分类号: H01J37/32422 , H01J37/32018 , H01J37/32091 , H01J37/3244 , H01J37/32522 , H01J37/32834 , H01J2237/2001 , H01J2237/334 , H01J2237/3344 , H01L21/67069 , Y10S156/915
摘要: A plasma processing apparatus includes a first and second electrodes disposed on upper and lower sides and opposite each other within a process container, a first RF power application unit and a DC power supply both connected to the first electrode, and second and third radio frequency power application units both connected to the second electrode. A conductive member is disposed within the process container and grounded to release through plasma a current caused by a DC voltage applied from the DC power supply. The conductive member is supported by a first shield part around the second electrode and laterally protruding therefrom at a position between the mount face of the second electrode and an exhaust plate for the conductive member to be exposed to the plasma. The conductive member is grounded through a conductive internal body of the first shield part.
摘要翻译: 一种等离子体处理装置,包括在处理容器内设置在上侧和下侧并彼此相对的第一和第二电极,连接到第一电极的第一RF电力施加单元和DC电源,以及第二和第三射频功率 应用单元都连接到第二电极。 导电构件设置在处理容器内并接地以通过等离子体释放由直流电源施加的直流电压引起的电流。 导电构件由第二电极周围的第一屏蔽部分支撑,并且在第二电极的安装面和用于导电构件的排气板之间的位置处侧向突出以暴露于等离子体。 导电构件通过第一屏蔽部分的导电内部主体接地。
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