Method of simultaneously forming contacts to a power rail and the source and drain regions of a FinFET

    公开(公告)号:US11282753B2

    公开(公告)日:2022-03-22

    申请号:US16963362

    申请日:2019-01-21

    发明人: Kazuo Kibi

    摘要: In a method for manufacturing a semiconductor device that comprises a semiconductor fin including a source region and a drain region, which configure a field effect transistor, and a fixed potential line provided in parallel to the semiconductor fin, the method comprises: a first step of preparing an intermediate body in which an insulating layer is provided on the source region (P-type conductive region), the drain region (N-type conductive region), and the fixed potential line; and a second step of simultaneously forming contact holes leading to the source region, the drain region, and the fixed potential line, in the insulating layer.

    Method of manufacturing semiconductor device

    公开(公告)号:US12100616B2

    公开(公告)日:2024-09-24

    申请号:US17445436

    申请日:2021-08-19

    IPC分类号: H01L21/768 H01L21/027

    摘要: A method of manufacturing a semiconductor device includes: planarizing a surface of a substrate having a conductive material embedded in a first hole so as to expose the conductive material embedded in the first hole, wherein the first hole is formed in a region which is on an insulating film laminated on the substrate and is surrounded by a spacer film; laminating a mask film on the surface of the substrate; forming a second hole in the mask film such that at least a portion of an upper surface of the conductive material embedded in the first hole is exposed; embedding the conductive material in the second hole; and removing the mask film.