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33 条记录 (耗时 0.042 秒)

    Three-state output circuit
    3.
    发明授权
    Three-state output circuit 失效
    三态输出电路

    公开(公告)号：US4322640A

    公开(公告)日：1982-03-30

    申请号：US95073

    申请日：1979-11-16

    申请人： Toshitaka Fukushima ,  Kouji Ueno

    发明人： Toshitaka Fukushima ,  Kouji Ueno

    IPC分类号： G11C17/00 ,  G11C11/41 ,  G11C11/416 ,  G11C17/08 ,  G11C17/14 ,  H01L21/822 ,  H01L27/04 ,  H03K19/018 ,  H03K19/082 ,  H03K19/20

    CPC分类号： G11C17/08 ,  H03K19/01806 ,  H03K19/0826

    摘要： A three-state output circuit is disclosed. The three-state output circuit is comprised of a phase-splitter transistor, a pull-up transistor and a pull-down transistor and further comprised of a control circuit which operates to make the transistors active or non-active. At least one of said transistors is connected to the control circuit via a newly employed PNP transistor through its emitter and base. The collector thereof is connected to a ground point of the three-state output circuit.

    摘要翻译： 公开了一种三态输出电路。 三态输出电路由分相晶体管，上拉晶体管和下拉晶体管组成，并且还包括一个控制电路，其操作以使晶体管工作或非有效。 所述晶体管中的至少一个通过新近采用的PNP晶体管通过其发射极和基极连接到控制电路。 其集电极连接到三态输出电路的接地点。

    Field programmable device with circuitry for detecting poor insulation between adjacent word lines
    5.
    发明授权
    Field programmable device with circuitry for detecting poor insulation between adjacent word lines 失效
    具有用于检测相邻字线之间绝缘不良的电路的现场可编程器件

    公开(公告)号：US4459694A

    公开(公告)日：1984-07-10

    申请号：US333653

    申请日：1981-12-23

    申请人： Kouji Ueno ,  Toshitaka Fukushima ,  Kazumi Koyama

    发明人： Kouji Ueno ,  Toshitaka Fukushima ,  Kazumi Koyama

    IPC分类号： G11C29/00 ,  G11C17/00 ,  G11C29/04 ,  G11C29/24 ,  H01L21/66 ,  H01L21/822 ,  H01L21/8229 ,  H01L27/04 ,  H01L27/102 ,  G06F11/22

    CPC分类号： G11C29/24 ,  G11C29/04

    摘要： A field programmable device comprises regular word lines, regular bit lines, regular memory cells connected at the intersections of the regular word lines and the regular bit lines, at least one test word line adjacent to one of the regular bit lines, and alternately arranged conducting and nonconducting test memory cells arranged at the intersections of the test bit lines and the regular word lines. According to the invention, for the purpose of determining poor insulation between the word lines, the test bit line and the regular word line are insulated by an insulating layer in each nonconducting test memory cell.

    摘要翻译： 现场可编程设备包括常规字线，规则位线，连接在正常字线和规则位线的交点处的常规存储器单元，至少一个与常规位线之一相邻的测试字线，并且交替排列导电 以及布置在测试位线和常规字线的交点处的非导体测试存储单元。 根据本发明，为了确定字线之间的差的绝缘，测试位线和常规字线在每个非导通测试存储单元中被绝缘层绝缘。

    Semiconductor memory device
    7.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4424582A

    公开(公告)日：1984-01-03

    申请号：US141931

    申请日：1980-04-21

    申请人： Toshitaka Fukushima ,  Kazumi Koyama ,  Kouji Ueno ,  Tamio Miyamura ,  Yuichi Kawabata

    发明人： Toshitaka Fukushima ,  Kazumi Koyama ,  Kouji Ueno ,  Tamio Miyamura ,  Yuichi Kawabata

    IPC分类号： G11C17/00 ,  G11C17/06 ,  G11C17/08 ,  G11C17/14 ,  G11C17/18 ,  G11C7/00

    CPC分类号： G11C17/18 ,  G11C17/08

    摘要： A semiconductor memory device which writes information by rendering particular memory cells conductive or non-conductive, wherein, when a selected memory cell is to be read out, a power supply voltage is applied to the collector of a transistor which feeds a base current to a final stage transistor of a decoder circuit which is connected to word lines, and when information is to be written in, a voltage higher than the power supply voltage is applied to the same collector.

    摘要翻译： 一种半导体存储器件，其通过使特定的存储器单元导电或不导电地写信息，其中当要读出所选存储单元时，将电源电压施加到晶体管的集电极，晶体管馈送基极电流至 连接到字线的解码器电路的最后级晶体管，并且当要写入信息时，将高于电源电压的电压施加到同一个集电极。

    Field programmable device having test provisions for fault detection
    8.
    发明授权
    Field programmable device having test provisions for fault detection 失效
    具有故障检测测试条件的现场可编程器件

    公开(公告)号：US4320507A

    公开(公告)日：1982-03-16

    申请号：US95782

    申请日：1979-11-19

    申请人： Toshitaka Fukushima ,  Kazumi Koyama ,  Kouji Ueno

    发明人： Toshitaka Fukushima ,  Kazumi Koyama ,  Kouji Ueno

    IPC分类号： G11C17/00 ,  G11C29/00 ,  G11C29/24 ,  G11C29/52 ,  G06F11/22 ,  G01R31/26

    CPC分类号： G11C29/52 ,  G11C29/24

    摘要： A field programmable device having a memory cell member including regular bit lines, regular word lines, regular memory cells connected at the cross points of said regular bit lines and regular word lines, test bit or test word lines, and non-conductive and conductive test memory cells connected at the cross points of said regular bit or regular word lines and test word or test bit lines, wherein the conductivity of a test memory cell is determined by the "1" or "0" of the address signal by which the test word or test bit line to which the test memory cell is connected is selected.

    摘要翻译： 一种具有存储单元构件的现场可编程装置，包括常规位线，常规字线，在所述规则位线和规则字线的交叉点处连接的常规存储单元，测试位或测试字线，以及非导电和导电测试 在所述规则位或常规字线和测试字或测试位线的交叉点处连接的存储单元，其中测试存储单元的电导率由地址信号的“1”或“0”确定， 选择测试存储单元连接到的字或测试位线。

    Semiconductor memory device utilizing multi-stage decoding
    9.
    发明授权
    Semiconductor memory device utilizing multi-stage decoding 失效
    半导体存储器件利用多级解码

    公开(公告)号：US4617653A

    公开(公告)日：1986-10-14

    申请号：US566323

    申请日：1983-12-28

    申请人： Yasuro Matsuzaki ,  Toshitaka Fukushima ,  Kouji Ueno

    发明人： Yasuro Matsuzaki ,  Toshitaka Fukushima ,  Kouji Ueno

    IPC分类号： G11C11/41 ,  G11C8/10 ,  G11C8/12 ,  G11C11/413 ,  G11C8/00 ,  G11C11/36

    CPC分类号： G11C8/10 ,  G11C8/12

    摘要： A semiconductor memory device includes a plurality of memory cells arranged in a matrix form and a decoder circuit selecting a row of the matrix in response to an address signal. The decoder circuit includes a first-stage decoder having a plurality of first-stage decoding elements and a second-stage decoder having a plurality of second-stage decoding elements. Each first-stage decoding element is connected to a plurality of second-stage decoding elements. Each of the first-stage decoding elements receives predetermined higher bits of the address signals. One of the first-stage decoding elements is selected upon one access command. Each of the plurality of second-stage decoding elements receives the address signals. One of the rows of the matrix is selected in response to the the address signals when the corresponding first-stage decoding element operates, whereby the power consumption is reduced.

    摘要翻译： 半导体存储器件包括以矩阵形式排列的多个存储器单元，以及响应于地址信号选择矩阵行的解码器电路。 解码器电路包括具有多个第一级解码元件的第一级解码器和具有多个第二级解码元件的第二级解码器。 每个第一级解码元件连接到多个第二级解码元件。 每个第一级解码元件接收地址信号的预定较高位。 一个访问命令选择第一级解码元素之一。 多个第二级解码元件中的每一个接收地址信号。 响应于相应的第一级解码元件操作时的地址信号，选择矩阵的行之一，从而降低功耗。

    Programmable read-only memory device
    10.
    发明授权
    Programmable read-only memory device 失效
    可编程只读存储器件

    公开(公告)号：US4376984A

    公开(公告)日：1983-03-15

    申请号：US137959

    申请日：1980-04-07

    申请人： Toshitaka Fukushima ,  Kazumi Koyama ,  Kouji Ueno

    发明人： Toshitaka Fukushima ,  Kazumi Koyama ,  Kouji Ueno

    IPC分类号： G11C17/06 ,  G11C17/14 ,  G11C17/16 ,  H01L21/8229 ,  H01L23/525 ,  H01L27/10 ,  H01L27/102 ,  H01L29/45 ,  G11C11/40

    CPC分类号： H01L23/5252 ,  G11C17/16 ,  H01L27/10 ,  H01L29/456 ,  H01L2924/0002

    摘要： A PROM (programmable read-only memory) device includes both PROM cells and peripheral circuits cooperating therewith with the PROM cells and peripheral circuits formed in and on the same bulk. The bulk is formed free of metal which acts as a life time killer. Further, in each of the PROM cells, a buffer layer made of a silicon semiconductor, is introduced between a metal electrode, acting as a bit line, and the surface of the bulk at the position where the PROM cell is formed. Furthermore, the peripheral circuits are made by using Schottky TTL (transistor transistor logic) circuits.

    摘要翻译： PROM（可编程只读存储器）装置包括PROM单元和与PROM单元协同工作的外围电路和在相同体积上形成的外围电路。 该体积不含作为寿命杀手的金属。 此外，在每个PROM单元中，将由硅半导体制成的缓冲层引入作为位线的金属电极和在形成PROM单元的位置处的体的表面之间。 此外，通过使用肖特基TTL（晶体管晶体管逻辑）电路来制造外围电路。