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公开(公告)号：US06335566B1
公开(公告)日：2002-01-01
申请号：US09646712
申请日：2000-11-30
IPC分类号： H01L2302
CPC分类号： H01L24/97 , H01L23/49838 , H01L23/50 , H01L23/642 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16225 , H01L2224/16265 , H01L2224/73204 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/14 , H01L2924/15151 , H01L2924/15153 , H01L2924/15159 , H01L2924/15173 , H01L2924/15174 , H01L2924/15311 , H01L2924/15787 , H01L2924/19041 , H01L2924/19103 , H01L2924/19104 , H01L2924/30107 , H01L2224/81 , H01L2924/00 , H01L2224/05599
摘要： Disclosed herein is a semiconductor device in which a main surface of a semiconductor chip is placed over a first main surface of a wiring board so as to be opposed thereto and which includes a plurality of external terminals provided over a second main surface of the wiring board. The plurality of external terminals have a plurality of signal terminals and a plurality of power terminals. The signal terminals are arranged along the periphery of the wiring board and the power terminals are arranged along the inside of a row of the signal terminals. Chip capacitors are placed over the main surface of the semiconductor chip, which lies inside a row of the power terminals. The plurality of signal terminals and power terminals formed over the main surface of the semiconductor chip are connected to a plurality of wires formed over the wiring board respectively. The wiring board is provided with an opening or recess which extends therethrough. The chip capacitors are located within the opening or recess. Thus, a reduction in switching noise can be achieved.
摘要翻译： 这里公开了一种半导体器件，其中半导体芯片的主表面被布置在布线板的与其相对的第一主表面上方，并且包括设置在布线板的第二主表面上的多个外部端子 。 多个外部端子具有多个信号端子和多个电源端子。 信号端子沿着布线板的周边布置，并且电源端子沿着信号端子的一行的内侧布置。 芯片电容器放置在半导体芯片的主表面上，该主表面位于一排电源端子内。 形成在半导体芯片的主表面上的多个信号端子和电源端子分别连接到布线板上形成的多条电线。 布线板设置有从其延伸穿过的开口或凹槽。 芯片电容器位于开口或凹槽内。 因此，可以实现开关噪声的降低。
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公开(公告)号：US06996377B1
公开(公告)日：2006-02-07
申请号：US09787380
申请日：1999-09-14
IPC分类号： H04B1/40
CPC分类号： H03L7/10 , H03D13/007 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/12 , H04B1/406
摘要： In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.
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公开(公告)号：US06970683B2
公开(公告)日：2005-11-29
申请号：US10375241
申请日：2003-02-28
IPC分类号： H03L7/10 , H03D13/00 , H03L7/00 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/107 , H03L7/16 , H03L7/18 , H04B1/3822 , H04B1/40 , H04L7/033
CPC分类号： H03L7/10 , H03D13/007 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/12 , H04B1/406
摘要： In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.
摘要翻译： 在PLL电路中，将LPF的数量减少到一个，以减少安装面积和引脚数量，并简化设计。 在一个实施例中，PLL电路包括可变增益相位比较器，混频器，LPF，VCO，耦合器以及控制VCO的开/关操作的控制电路。 可变增益相位比较器能够改变相位差增益。 VCO的操作的开/关由控制电路控制，使得VCO中的一个被关断。 相位差转换增益根据VCO的灵敏度而变化，因此PLL电路所需的LPF的数量可以减少到一个。
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公开(公告)号：US07333779B2
公开(公告)日：2008-02-19
申请号：US11121018
申请日：2005-05-04
CPC分类号： H03L7/10 , H03D13/007 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/12 , H04B1/406
摘要： In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.
摘要翻译： 在PLL电路中，将LPF的数量减少到一个，以减少安装面积和引脚数量，并简化设计。 在一个实施例中，PLL电路包括可变增益相位比较器，混频器，LPF，VCO，耦合器以及控制VCO的开/关操作的控制电路。 可变增益相位比较器能够改变相位差增益。 VCO的操作的开/关由控制电路控制，使得VCO中的一个被关断。 相位差转换增益根据VCO的灵敏度而变化，因此PLL电路所需的LPF的数量可以减少到一个。
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公开(公告)号：US20050215222A1
公开(公告)日：2005-09-29
申请号：US11121018
申请日：2005-05-04
IPC分类号： H03L7/10 , H03D13/00 , H03L7/00 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/107 , H03L7/16 , H03L7/18 , H04B1/3822 , H04B1/40 , H04L7/033
CPC分类号： H03L7/10 , H03D13/007 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/12 , H04B1/406
摘要： In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.
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公开(公告)号：US08138893B2
公开(公告)日：2012-03-20
申请号：US12057671
申请日：2008-03-28
申请人： Takefumi Endo , Takayuki Tsukamoto
发明人： Takefumi Endo , Takayuki Tsukamoto
IPC分类号： H04Q5/22
CPC分类号： H04B5/02 , H04B5/0031 , H04B5/0037
摘要： In an IC tag, when a semiconductor integrated circuit device is activated, an operation control unit sets existence/nonexistence of a communication distance limitation for reducing a communication distance to a state management unit. If the communication distance limitation is not set, a switch unit is turned ON and a demodulated command is inputted from a command demodulation circuit to a command decode unit. If the communication distance limitation is set, a power intensity monitor unit judges whether the power of a rectification circuit is greater than or equal to a predetermined arbitrary field intensity. If the power is less than the predetermined arbitrary field intensity, the switch unit is turned OFF and various commands demodulated by the command demodulation circuit are not inputted to the command decode unit. As a result, the semiconductor integrated circuit device does not operate.
摘要翻译： 在IC标签中，当半导体集成电路器件被激活时，操作控制单元设置存在/不存在通信距离限制，以减少与状态管理单元的通信距离。 如果没有设定通信距离限制，则开关单元被接通，并且解调命令从命令解调电路输入到命令解码单元。 如果设置了通信距离限制，则功率强度监视单元判断整流电路的功率是否大于或等于预定的任意场强。 如果功率小于预定的任意场强，则切换单元关闭，并且由命令解调电路解调的各种命令不被输入到命令解码单元。 结果，半导体集成电路器件不工作。
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