公开(公告)号：US20130120599A1

公开(公告)日：2013-05-16

申请号：US13611311

申请日：2012-09-12

申请人： Tsung-Tse Chen ,  Chia-Lin Hung ,  Huo-Wang Chou

发明人： Tsung-Tse Chen ,  Chia-Lin Hung ,  Huo-Wang Chou

IPC分类号： H04N5/228

CPC分类号： G03B5/00 ,  G03B2205/0038

摘要： A positionable mechanism includes a base unit, a frame unit, an optical image stabilizing (OIS) unit and a positioning unit. The frame unit and the OIS unit are mounted on the base unit. The frame unit is retractable with respect to the base unit between a storage position and a working position, and has a first surface. The OIS unit includes a movable carrier that has a second surface facing the first surface, an optical element that is mounted on the movable carrier, and a driving element that is operable to drive the movable carrier to move with respect to the base unit. The positioning unit is disposed between the first surface and the second surface, and is configured to position the movable carrier with respect to the frame unit when the frame unit is at the storage position.

摘要翻译： 可定位机构包括基座单元，框架单元，光学图像稳定（OIS）单元和定位单元。 框架单元和OIS单元安装在基座单元上。 框架单元相对于基座单元在存储位置和工作位置之间可伸缩，并且具有第一表面。 OIS单元包括可移动的载体，其具有面向第一表面的第二表面，安装在可移动载体上的光学元件和可操作以驱动可移动载体相对于基座单元移动的驱动元件。 定位单元设置在第一表面和第二表面之间，并且构造成当框架单元处于存储位置时相对于框架单元定位可移动托架。

公开(公告)号：US08976290B2

公开(公告)日：2015-03-10

申请号：US13611311

申请日：2012-09-12

申请人： Tsung-Tse Chen ,  Chia-Lin Hung ,  Huo-Wang Chou

发明人： Tsung-Tse Chen ,  Chia-Lin Hung ,  Huo-Wang Chou

IPC分类号： H04N5/225 ,  H04N5/228 ,  G03B5/00

CPC分类号： G03B5/00 ,  G03B2205/0038

摘要： A positionable mechanism includes a base unit, a frame unit, an optical image stabilizing (OIS) unit and a positioning unit. The frame unit and the OIS unit are mounted on the base unit. The frame unit is retractable with respect to the base unit between a storage position and a working position, and has a first surface. The OIS unit includes a movable carrier that has a second surface facing the first surface, an optical element that is mounted on the movable carrier, and a driving element that is operable to drive the movable carrier to move with respect to the base unit. The positioning unit is disposed between the first surface and the second surface, and is configured to position the movable carrier with respect to the frame unit when the frame unit is at the storage position.

摘要翻译： 可定位机构包括基座单元，框架单元，光学图像稳定（OIS）单元和定位单元。 框架单元和OIS单元安装在基座单元上。 框架单元相对于基座单元在存储位置和工作位置之间可伸缩，并且具有第一表面。 OIS单元包括可移动的载体，其具有面向第一表面的第二表面，安装在可移动载体上的光学元件和可操作以驱动可移动载体相对于基座单元移动的驱动元件。 定位单元设置在第一表面和第二表面之间，并且构造成当框架单元处于存储位置时相对于框架单元定位可移动托架。

公开(公告)号：US20130175324A1

公开(公告)日：2013-07-11

申请号：US13348503

申请日：2012-01-11

申请人： Hui-Shan Chang ,  Chia-Lin Hung ,  Chung Chieh Huang

发明人： Hui-Shan Chang ,  Chia-Lin Hung ,  Chung Chieh Huang

IPC分类号： B23K20/02 ,  B23K37/00

CPC分类号： H01L24/75 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/75303 ,  H01L2224/7531 ,  H01L2224/75312 ,  H01L2224/75745 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/0401

摘要： The present invention provides a method and a thermal compression head for flip chip bonding. The thermal compression head includes a main body and a contact portion. The main body has a main body opening. The contact portion has a contact surface and a plurality of openings. The openings communicate with the main body opening. When the contact surface of the contact portion is used to adsorb a chip, the contact surface of the chip has a plurality of adsorbed zones corresponding to the contact surface openings. After the chip is bonded to a substrate, the protrusions of the adsorbed zones are relatively slight. Therefore, the interconnection between the chip and the substrate is ensured.

摘要翻译： 本发明提供一种用于倒装芯片接合的方法和热压头。 热压头包括主体和接触部。 主体具有主体开口。 接触部分具有接触表面和多个开口。 开口与主体开口连通。 当接触部分的接触表面用于吸附芯片时，芯片的接触表面具有对应于接触表面开口的多个吸附区域。 在将芯片粘合到基板上之后，吸附区域的突出部分相对较小。 因此，确保了芯片和基板之间的互连。

公开(公告)号：US20110300669A1

公开(公告)日：2011-12-08

申请号：US12795315

申请日：2010-06-07

申请人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Chia-Lin Hung ,  Ying-Sheng Chuang

发明人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Chia-Lin Hung ,  Ying-Sheng Chuang

IPC分类号： H01L21/50

CPC分类号： H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73104 ,  H01L2224/81193 ,  H01L2224/83193 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

摘要： The present invention relates to a method for making chip assemblies, including the following steps of: (a) providing a tested upper wafer and at least one tested lower wafer; (b) sawing the at least one tested lower wafer to form a plurality of lower dice, the lower dice including a plurality of know good lower dice; (c) picking up and rearranging the know good lower dice on a carrier according to the wafer map of the upper wafer; (d) bonding the upper wafer and the carrier; (e) removing the carrier; and (f) proceeding sawing step. Whereby, the dice of the die assembly are both known good dice, thus the yield loss caused by the different yields between the upper wafer and the lower wafer will not occur.

摘要翻译： 本发明涉及一种制造芯片组件的方法，包括以下步骤：（a）提供测试的上晶片和至少一个经测试的下晶片; （b）锯切所述至少一个经测试的下晶片以形成多个下骰子，所述下骰子包括多个熟知的较低骰子; （c）根据上晶片的晶片图拾取并重新排列载体上的已知的较好的下骰子; （d）粘合上晶片和载体; （e）清除载体; 和（f）进行锯切步骤。 由此，芯片组件的裸片都是已知的好的裸片，因此不会发生由上晶片和下晶片之间的不同产量引起的屈服损失。

公开(公告)号：US08446000B2

公开(公告)日：2013-05-21

申请号：US12785704

申请日：2010-05-24

申请人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Tommy Pan ,  Hui-Shan Chang ,  Chia-Lin Hung

发明人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Tommy Pan ,  Hui-Shan Chang ,  Chia-Lin Hung

IPC分类号： H01L23/02 ,  H01L21/50

CPC分类号： H01L23/3135 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83

摘要： A package process includes following steps. A circuit mother board comprising a plurality of circuit boards is disposed on a carrier. Semiconductor devices are provided, wherein each of the semiconductor devices has a top surface and a bottom surface opposite thereto. Each of the semiconductor devices has conductive vias each having a first end surface and a second end surface exposed by the bottom surface of the semiconductor device. The semiconductor devices are connected to the corresponding circuit boards through their conductive vias with their bottom surface facing the circuit mother board. An insulating paste is formed between each of the semiconductor devices and its corresponding circuit board. A protection layer is formed on the circuit mother board to cover the semiconductor devices. Then, the protection layer and the semiconductor devices are thinned to expose the first end surface of each of the conductive vias.

摘要翻译： 包过程包括以下步骤。 包括多个电路板的电路母板设置在载体上。 提供半导体器件，其中每个半导体器件具有与其相对的顶表面和底表面。 每个半导体器件具有各自具有由半导体器件的底表面暴露的第一端面和第二端面的导电通孔。 半导体器件通过其导电通孔连接到相应的电路板，其底表面面向电路母板。 在每个半导体器件及其相应的电路板之间形成绝缘膏。 在电路母板上形成保护层以覆盖半导体器件。 然后，保护层和半导体器件变薄以暴露每个导电通孔的第一端面。

公开(公告)号：US20120175767A1

公开(公告)日：2012-07-12

申请号：US13311364

申请日：2011-12-05

申请人： Chia-Lin Hung ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Kuo-Pin Yang

发明人： Chia-Lin Hung ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Kuo-Pin Yang

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L24/14 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05155 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/29036 ,  H01L2224/2919 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/0665 ,  H01L2924/01047 ,  H01L2224/81 ,  H01L2224/80213 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： The present invention relates to a stacked semiconductor package and a method for making the same. The method includes the steps of mounting a plurality of first dice to a wafer by conducting a reflow process; and thinning the wafer from the backside surface of the wafer, thereby reducing manufacturing time and preventing warpage.

摘要翻译： 本发明涉及堆叠式半导体封装及其制造方法。 该方法包括通过进行回流处理将多个第一骰子安装到晶片的步骤; 并且从晶片的背面使晶片变薄，从而减少制造时间并防止翘曲。

公开(公告)号：US08643167B2

公开(公告)日：2014-02-04

申请号：US13311364

申请日：2011-12-05

申请人： Chia-Lin Hung ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Kuo-Pin Yang

发明人： Chia-Lin Hung ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Kuo-Pin Yang

IPC分类号： H01L23/04 ,  H01L23/34

CPC分类号： H01L24/14 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05155 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/29036 ,  H01L2224/2919 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/0665 ,  H01L2924/01047 ,  H01L2224/81 ,  H01L2224/80213 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： The present invention relates to a stacked semiconductor package and a method for making the same. The method includes the steps of mounting a plurality of first dice to a wafer by conducting a reflow process; and thinning the wafer from the backside surface of the wafer, thereby reducing manufacturing time and preventing warpage.

摘要翻译： 本发明涉及堆叠式半导体封装及其制造方法。 该方法包括通过进行回流处理将多个第一骰子安装到晶片的步骤; 并且从晶片的背面使晶片变薄，从而减少制造时间并防止翘曲。

公开(公告)号：US20110121442A1

公开(公告)日：2011-05-26

申请号：US12785704

申请日：2010-05-24

申请人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Tommy Pan ,  Hui-Shan Chang ,  Chia-Lin Hung

发明人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Tommy Pan ,  Hui-Shan Chang ,  Chia-Lin Hung

IPC分类号： H01L23/02 ,  H01L21/50

CPC分类号： H01L23/3135 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83

摘要： A package process includes following steps. A circuit mother board comprising a plurality of circuit boards is disposed on a carrier. Semiconductor devices are provided, wherein each of the semiconductor devices has a top surface and a bottom surface opposite thereto. Each of the semiconductor devices has conductive vias each having a first end surface and a second end surface exposed by the bottom surface of the semiconductor device. The semiconductor devices are connected to the corresponding circuit boards through their conductive vias with their bottom surface facing the circuit mother board. An insulating paste is formed between each of the semiconductor devices and its corresponding circuit board. A protection layer is formed on the circuit mother board to cover the semiconductor devices. Then, the protection layer and the semiconductor devices are thinned to expose the first end surface of each of the conductive vias.

摘要翻译： 包过程包括以下步骤。 包括多个电路板的电路母板设置在载体上。 提供半导体器件，其中每个半导体器件具有与其相对的顶表面和底表面。 每个半导体器件具有各自具有由半导体器件的底表面暴露的第一端面和第二端面的导电通孔。 半导体器件通过其导电通孔连接到相应的电路板，其底表面面向电路母板。 在每个半导体器件及其相应的电路板之间形成绝缘膏。 在电路母板上形成保护层以覆盖半导体器件。 然后，保护层和半导体器件变薄以暴露每个导电通孔的第一端面。