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公开(公告)号:US10924002B2
公开(公告)日:2021-02-16
申请号:US16676470
申请日:2019-11-07
Inventor: Zekun Zhou , Junyuan Rong , Zuao Wang , Yue Shi , Zhuo Wang , Bo Zhang
Abstract: A transient response enhancement circuit for buck-type voltage converters, wherein, the transient load changing detecting module detects the output voltage of the buck-type voltage converter. The first control signal is generated when the increase of the output voltage is detected, and the second control signal is generated when the decrease of the output voltage is detected, thereby self-adaptively detecting the time of the buck-type voltage converter in response to the load changing. The compensation voltage predicting operation module predicts and adjusts the compensation voltage and the adjusted compensation voltage is superimposed on the buck-type voltage converter through the internal active compensation module to adjust the duty ratio of the buck-type voltage converter. The drive controlling insertion logic module can further improve the response speed.
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公开(公告)号:US10911045B1
公开(公告)日:2021-02-02
申请号:US17005350
申请日:2020-08-28
IPC: H03K17/687
Abstract: A segmented direct gate drive circuit of a depletion mode GaN power device, a gate voltage of the GaN power device is charged from a negative voltage turn-off level to a threshold voltage of the GaN power device; when the gate voltage of the GaN power device is charged to the threshold voltage of the GaN power device, a current mirror charging module first turns on less than N of charging current mirror modules to charge the gate voltage of the GaN power device from the threshold voltage of the GaN power device to a Miller platform voltage of the GaN power device, and turns on N charging current mirror modules to charge the gate voltage of the GaN power device from the Miller platform voltage of the GaN power device to a zero level.
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公开(公告)号:US10530258B1
公开(公告)日:2020-01-07
申请号:US16392664
申请日:2019-04-24
Inventor: Zekun Zhou , Yunkun Wang , Yandong Yuan , Shilei Li , Zhuo Wang , Bo Zhang
Abstract: A predictive dead time generating circuit includes a dead time detecting module configured to detect a dead time between the switching off of the upper power transistor and the switching on of the lower power transistor, and a dead time between the switching off of the lower power transistor and the switching on of the upper power transistor, and to generate a first detecting signal and a second detecting signal according to the condition of whether the detected dead time reaches an optimal value. The logic control module changes the output of the delay module according to the judgment result of the dead time detecting module, so as to change the dead time between the driving signal of the upper power transistor and the driving signal of the lower power transistor.
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公开(公告)号:US10353417B2
公开(公告)日:2019-07-16
申请号:US16026081
申请日:2018-07-03
Applicant: University of Electronic Science and Technology of China , Institute of Electronic and Information Engineering of UESTC in Guangdong
Inventor: Xin Ming , Jiahao Zhang , Wenlin Zhang , Di Gao , Xuan Zhang , Zhuo Wang , Bo Zhang
Abstract: A ripple pre-amplification based fully integrated LDO pertains to the technical field of power management. The positive input terminal of a transconductance amplifier is connected to a reference voltage Vref, and the negative input terminal of the transconductance amplifier is connected to the feedback voltage Vfb. The output terminal of the transconductance amplifier is connected to the negative input terminal of a transimpedance amplifier and the negative input terminal of an error amplifier. The positive input terminal of the transimpedance amplifier is connected to the ground GND, and the output terminal of the transimpedance amplifier is connected to the positive input terminal of the error amplifier. The gate terminal of the power transistor MP is connected to the output terminal of the error amplifier, the source terminal of the power transistor MP is connected to an input voltage VIN, and the drain terminal of the power transistor MP is grounded.
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公开(公告)号:US09891644B1
公开(公告)日:2018-02-13
申请号:US15387678
申请日:2016-12-22
Inventor: Xin Ming , Tiansheng Li , Jun Xu , Zhuo Wang , Bo Zhang
Abstract: A low-dropout regulator, including: a dynamic pole tracking circuit having an active load, a voltage-to-current converter, a current amplifier, a bias circuit, a regulating transistor, a first feedback resistor, a second feedback resistor, and a first capacitor. The dynamic pole tracking circuit includes: a first PMOS, a second PMOS, a first resistor, and a second resistor. The voltage-to-current converter includes: a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, a fifth NMOS, a sixth NMOS, a seventh NMOS, an eighth NMOS, a third PMOS, a fourth PMOS, a seventh PMOS, an eighth PMOS. The current amplifier includes: a fifth PMOS, a sixth PMOS, a ninth NMOS, a tenth NMOS, and a third resistor. The bias circuit includes: a ninth PMOS, a tenth PMOS, an eleventh PMOS, an eleventh NMOS, a twelfth NMOS, a thirteenth NMOS, and a fourth resistor.
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公开(公告)号:US10374506B1
公开(公告)日:2019-08-06
申请号:US16174307
申请日:2018-10-30
Inventor: Ze-kun Zhou , Jun-Lin Qian , Xiao-Lin Liu , Yue Shi , Zhuo Wang , Bo Zhang
Abstract: An adaptive control method for zero voltage switching belongs to the field of integrated circuit. In the present invention, the difference between the turn-on time of the power tube and the time of the lowest drain voltage of the power tube in the switching cycle is quantified by the reversible counter, and the quantized result is transmitted to the next switching cycle to adjust the turn-on time of the power tube through the final count result of the reversible counter, so that the power tube after being adjusted can be turned on when the drain voltage of the power tube is the lowest, thus reducing the switching loss. The present invention can adaptively turn on the power tube when the drain voltage of the power tube reaches minimum, thus, realizing the zero-voltage switching, reducing the switching loss of the switching power supply, widening the application range.
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公开(公告)号:US10042379B1
公开(公告)日:2018-08-07
申请号:US15867717
申请日:2018-01-11
Inventor: Zekun Zhou , Xiang Li , Yandong Yuan , Yue Shi , Zhuo Wang , Bo Zhang
Abstract: A sub-threshold low-power and resistor-less reference circuit which is related to the field of reference circuit technology of analog circuit includes a negative-temperature-coefficient voltage generating circuit, a positive-temperature-coefficient voltage generating circuit and a current balancing circuit. The negative-temperature-coefficient voltage generating circuit generates a negative-temperature-coefficient voltage VCTAT based on the negative-temperature voltage characteristic of base-emitter PN junction of the bipolar tsansistor. On the other hand, the positive-temperature-coefficient voltage generating circuit generates a positive-temperature-coefficient voltage VPTAT based on the positive-temperature voltage characteristic of the NMOS transistor operating in a sub-threshold region. The current balancing circuit is configured to eliminate the error current caused due to the difference of the current mirror when the two voltages with different temperature characteristics are superposed to output a reference voltage.
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公开(公告)号:US10862463B1
公开(公告)日:2020-12-08
申请号:US16848864
申请日:2020-04-15
Inventor: Zekun Zhou , Jianwen Cao , Zhuo Wang , He Tang , Bo Zhang
IPC: H03K19/0185 , H03K3/356 , H03K3/012 , H03K5/134
Abstract: A level shifter includes a power supply rail conversion block, an RS latch and a digital detection block. The power supply rail conversion block comprises a first NLDMOS transistor, a second NLDMOS transistor, a first PLDMOS transistor, a second PLDMOS transistor, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first inverter. A gate of the first NLDMOS transistor is connected to an input of the first inverter, a drain of the first NLDMOS transistor is connected to a drain of the first PLDMOS transistor; a source of the first NLDMOS transistor and a source of the second NLDMOS are connected to a referenced ground of an LV power supply rail. The digital detection block comprises a second inverter, a third inverter, a first delay chain, a second delay chain, a first NAND gate and a second NAND gate.
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公开(公告)号:US10673426B2
公开(公告)日:2020-06-02
申请号:US16455803
申请日:2019-06-28
Inventor: Xin Ming , Li Hu , Xuan Zhang , Su Pan , Chunqi Zhang , Yao Qin , Zhiwen Zhang , Yangli Xin , Zhuo Wang , Bo Zhang
Abstract: A switch bootstrap charging circuit suitable for a gate drive circuit of a GaN power device includes a high-voltage MOSFET, a low-voltage MOSFET, a high-voltage MOSFET control module, and a low-voltage MOSFET control module. The low-voltage MOSFET is a PMOS transistor, and the source of the low-voltage MOSFET is connected to the power supply voltage. The drain of the high-voltage MOSFET serves as an output terminal of the switch bootstrap charging circuit. The low-voltage MOSFET control module and the high-voltage MOSFET control module generate a gate drive signal of the low-voltage MOSFET and a gate drive signal of the high-voltage MOSFET according to the gate drive signal of the lower power transistor.
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公开(公告)号:US10146238B2
公开(公告)日:2018-12-04
申请号:US15599484
申请日:2017-05-19
Inventor: Zekun Zhou , Yao Wang , Jianwen Cao , Hongming Yu , Yunkun Wang , Anqi Wang , Zhuo Wang , Bo Zhang
Abstract: A resistorless CMOS low power voltage reference circuit is provided. The start-up circuit is used to prevent the circuit to stay in the zero state and stop working when the circuit gets out of the zero state. The self-biased VPTAT generating circuit generate the voltage VPTAT which has positive temperature coefficient. The square-law current generating circuit generates a square-law current which is proportional to μT2 through the VPTAT. Finally, the reference voltage VREF is obtained by introducing the square-law current into the reference voltage output circuit. The reference voltage VREF of this application can realize approximative zero temperature coefficient in the temperature range of −40° C.˜100° C. This application improves temperature characteristic which may be poorer due to temperature nonlinearity of carrier mobility based on the traditional subthreshold reference. This application can reduce the power consumption from μW level to nW level and realize low power consumption.
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