公开(公告)号：US10068963B2

公开(公告)日：2018-09-04

申请号：US14936370

申请日：2015-11-09

Applicant: United Microelectronics Corp.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee ,  Yu-Ru Yang ,  Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Cheng-Tzung Tsai

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L21/225 ,  H01L21/768

Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.

公开(公告)号：US09871102B2

公开(公告)日：2018-01-16

申请号：US14684443

申请日：2015-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L21/02 ,  H01L29/10

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/3247 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/786

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.

公开(公告)号：US09698218B2

公开(公告)日：2017-07-04

申请号：US15221617

申请日：2016-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Sheng-Hao Lin ,  Huai-Tzu Chiang ,  Hao-Ming Lee

IPC: H01L29/06 ,  H01L21/02 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/324 ,  H01L21/306 ,  H01L29/10

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/3247 ,  H01L29/0669 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present invention provides some methods for forming at least two different nanowire structures with different diameters on one substrate. Since the diameter of the nanowire structure will influence the threshold voltage (Vt) and the drive currents of a nanowire field effect transistor, in this invention, at least two nanowire structures with different diameters can be formed on one substrate. Therefore, in the following steps, these nanowire structures can be applied in different nanowire field effect transistors with different Vt and drive currents. This way, the flexibility of the nanowire field effect transistors can be improved.

公开(公告)号：US09590041B1

公开(公告)日：2017-03-07

申请号：US14960430

申请日：2015-12-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ru Yang ,  Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Cheng-Tzung Tsai

IPC: H01L21/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/165 ,  H01L29/778 ,  H01L27/092

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/02538 ,  H01L27/092 ,  H01L29/105 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/785

Abstract: A semiconductor structure includes a semiconductor substrate, a dielectric structure formed on the semiconductor substrate and including at least a recess formed therein, a fin formed in the recess, and a dislocation region formed in the fin. The semiconductor substrate includes a first semiconductor material. The fin includes the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. A topmost portion of the dislocation region is higher than an opening of the recess.

Abstract translation: 半导体结构包括半导体衬底，形成在半导体衬底上并且至少包括形成在其中的凹部的电介质结构，形成在凹部中的鳍和形成在鳍中的位错区。 半导体衬底包括第一半导体材料。 翅片包括第一半导体材料和第二半导体材料。 第二半导体材料的晶格常数与第一半导体材料的晶格常数不同。 位错区域的最高部分高于凹部的开口。

公开(公告)号：US20160268375A1

公开(公告)日：2016-09-15

申请号：US14684443

申请日：2015-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/10 ,  H01L29/423 ,  H01L21/311 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/3247 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/786

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.

Abstract translation: 半导体器件及其形成方法，该半导体器件包括单晶衬底，源/漏结构和纳米线结构。 源极/漏极结构设置在衬底上并与衬底接触。 纳米线结构连接到源极/漏极结构。

公开(公告)号：US12224338B2

公开(公告)日：2025-02-11

申请号：US17214932

申请日：2021-03-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Yi-Chun Chan

IPC: H01L21/31 ,  H01L21/311 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78

Abstract: An HEMT includes a gallium nitride layer. An aluminum gallium nitride layer is disposed on the gallium nitride layer. A gate is disposed on the aluminum gallium nitride layer. The gate includes a P-type gallium nitride and a schottky contact layer. The P-type gallium nitride contacts the schottky contact layer, and a top surface of the P-type gallium nitride entirely overlaps a bottom surface of the schottky contact layer. A protective layer covers the aluminum gallium nitride layer and the gate. A source electrode is disposed at one side of the gate, penetrates the protective layer and contacts the aluminum gallium nitride layer. A drain electrode is disposed at another side of the gate, penetrates the protective layer and contacts the aluminum gallium nitride layer. A gate electrode is disposed directly on the gate, penetrates the protective layer and contacts the schottky contact layer.

公开(公告)号：US11843046B2

公开(公告)日：2023-12-12

申请号：US17145414

申请日：2021-01-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Kuan-Hung Liu

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7786 ,  H01L29/42316 ,  H01L29/452 ,  H01L29/66431 ,  H01L29/0843 ,  H01L29/66462

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer, a carrier transit layer, a carrier supply layer, a gate, a source electrode and a drain electrode. The buffer layer is on a substrate. The carrier transit layer is on the buffer layer. The carrier supply layer is on the carrier transit layer. The gate is on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the gate, wherein each of the source electrode and the drain electrode includes a conductive layer and a conductive oxide layer stacked from bottom to top.

公开(公告)号：US10431652B2

公开(公告)日：2019-10-01

申请号：US15834082

申请日：2017-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L29/10 ,  H01L29/775 ,  B82Y10/00 ,  H01L21/324

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.

公开(公告)号：US20170098692A1

公开(公告)日：2017-04-06

申请号：US14936370

申请日：2015-11-09

Applicant: United Microelectronics Corp.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee ,  Yu-Ru Yang ,  Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Cheng-Tzung Tsai

IPC: H01L29/06 ,  H01L21/768 ,  H01L29/66 ,  H01L21/225 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/0615 ,  H01L21/2253 ,  H01L21/76802 ,  H01L21/76871 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.

公开(公告)号：US09502519B2

公开(公告)日：2016-11-22

申请号：US14636125

申请日：2015-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Sheng-Hao Lin ,  Huai-Tzu Chiang ,  Hao-Ming Lee

IPC: H01L21/336 ,  H01L29/792 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/7827

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first dielectric layer and a second dielectric layer thereon; forming a drain layer in the first dielectric layer and the second dielectric layer; forming a gate layer on the second dielectric layer; forming a channel layer in the gate layer; forming a third dielectric layer and a fourth dielectric layer on the gate layer and the channel layer; and forming a source layer in the third dielectric layer and the fourth dielectric layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有第一介电层和第二介电层的基板; 在所述第一电介质层和所述第二电介质层中形成漏极层; 在所述第二电介质层上形成栅极层; 在栅极层中形成沟道层; 在栅极层和沟道层上形成第三电介质层和第四电介质层; 以及在所述第三电介质层和所述第四电介质层中形成源极层。