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12 条记录 (耗时 0.025 秒)

    Deposition method for transition-metal oxide based dielectric
    5.
    发明申请
    Deposition method for transition-metal oxide based dielectric 审中-公开
    基于过渡金属氧化物的电介质的沉积方法

    公开(公告)号：US20080182427A1

    公开(公告)日：2008-07-31

    申请号：US11698337

    申请日：2007-01-26

    申请人： Lars Oberbeck ,  Uwe Schroeder ,  Johannes Heitmann ,  Stephan Kudelka ,  Tim Boescke ,  Jonas Sundqvist

    发明人： Lars Oberbeck ,  Uwe Schroeder ,  Johannes Heitmann ,  Stephan Kudelka ,  Tim Boescke ,  Jonas Sundqvist

    IPC分类号： H01L29/78 ,  H01L21/31 ,  H01L29/92

    CPC分类号： H01L21/02337 ,  H01L21/02175 ,  H01L21/28194 ,  H01L21/3142 ,  H01L21/31641 ,  H01L27/10805 ,  H01L27/1085 ,  H01L28/40 ,  H01L29/513 ,  H01L29/517

    摘要： The present invention relates to a method for depositing a dielectric material comprising a transition metal oxide. In an initial step, a substrate is provided. In a further step, a first precursor comprising a transition metal containing compound, and a second precursor predominantly comprising at least one of water vapor, ozone, oxygen, or oxygen plasma are sequentially applied for depositing above the substrate a layer of a transition metal containing material. In another step, a third precursor comprising a dopant containing compound, and a fourth precursor predominantly comprising at least one of water vapor, ozone, oxygen, or oxygen plasma are sequentially applied for depositing above the substrate a layer of a dopant containing material. The transition metal comprises at least one of zirconium and hafnium. The dopant comprises at least one of barium, strontium, calcium, niobium, bismuth, magnesium, and cerium.

    摘要翻译： 本发明涉及沉积包含过渡金属氧化物的电介质材料的方法。 在初始步骤中，提供衬底。 在另一步骤中，依次施加包含含过渡金属的化合物的第一前体和主要包含水蒸气，臭氧，氧或氧等离子体中的至少一种的第二前体，以在基底上沉积含有过渡金属的层 材料。 在另一步骤中，顺序地施加包含掺杂剂的化合物的第三前体和主要包含水蒸汽，臭氧，氧或氧等离子体中的至少一种的第四前体，以在衬底上沉积含掺杂剂材料的层。 过渡金属包括锆和铪中的至少一种。 掺杂剂包括钡，锶，钙，铌，铋，镁和铈中的至少一种。

    Integrated circuit with dielectric layer
    6.
    发明授权
    Integrated circuit with dielectric layer 有权
    集成电路与介质层

    公开(公告)号：US07709359B2

    公开(公告)日：2010-05-04

    申请号：US11850218

    申请日：2007-09-05

    申请人： Tim Boescke ,  Johannes Heitmann ,  Uwe Schroder

    发明人： Tim Boescke ,  Johannes Heitmann ,  Uwe Schroder

    IPC分类号： H01L29/72

    CPC分类号： H01L21/28291 ,  H01L27/10873 ,  H01L28/40 ,  H01L28/91 ,  H01L29/513 ,  H01L29/78

    摘要： A method of fabricating an integrated circuit with a dielectric layer on a substrate is disclosed. One embodiment provides forming the dielectric layer in an amorphous state on the substrate, the dielectric layer having a crystallization temperature; a doping the dielectric layer; a forming of a covering layer on the dielectric layer at a temperature being equal to or below the crystallization temperature; and a heating of the dielectric layer to a temperature being equal to or greater than the crystallization temperature.

    摘要翻译： 公开了一种在衬底上制造具有电介质层的集成电路的方法。 一个实施例提供在基底上形成非晶状态的电介质层，介电层具有结晶温度; 掺杂介电层; 在等于或低于结晶温度的温度下在电介质层上形成覆盖层; 以及将介电层加热至等于或大于结晶温度的温度。

    INTEGRATED CIRCUIT WITH DIELECTRIC LAYER
    7.
    发明申请
    INTEGRATED CIRCUIT WITH DIELECTRIC LAYER 有权
    集成电路与电介质层

    公开(公告)号：US20090057737A1

    公开(公告)日：2009-03-05

    申请号：US11850218

    申请日：2007-09-05

    申请人： Tim Boescke ,  Johannes Heitmann ,  Uwe Schroder

    发明人： Tim Boescke ,  Johannes Heitmann ,  Uwe Schroder

    IPC分类号： H01L29/76 ,  H01L21/00

    CPC分类号： H01L21/28291 ,  H01L27/10873 ,  H01L28/40 ,  H01L28/91 ,  H01L29/513 ,  H01L29/78

    摘要： A method of fabricating an integrated circuit with a dielectric layer on a substrate is disclosed. One embodiment provides forming the dielectric layer in an amorphous state on the substrate, the dielectric layer having a crystallization temperature; a doping the dielectric layer; a forming of a covering layer on the dielectric layer at a temperature being equal to or below the crystallization temperature; and a heating of the dielectric layer to a temperature being equal to or greater than the crystallization temperature.

    摘要翻译： 公开了一种在衬底上制造具有电介质层的集成电路的方法。 一个实施例提供在基底上形成非晶状态的电介质层，介电层具有结晶温度; 掺杂介电层; 在等于或低于结晶温度的温度下在电介质层上形成覆盖层; 以及将介电层加热至等于或大于结晶温度的温度。

    Storage capacitor for semiconductor memory cells and method of manufacturing a storage capacitor
    8.
    发明申请
    Storage capacitor for semiconductor memory cells and method of manufacturing a storage capacitor 失效
    用于半导体存储单元的存储电容器和制造存储电容器的方法

    公开(公告)号：US20070170487A1

    公开(公告)日：2007-07-26

    申请号：US11339744

    申请日：2006-01-25

    申请人： Johannes Heitmann ,  Peter Moll ,  Odo Wunnicke ,  Till Schloesser

    发明人： Johannes Heitmann ,  Peter Moll ,  Odo Wunnicke ,  Till Schloesser

    IPC分类号： H01L27/108 ,  H01L21/20

    CPC分类号： H01L28/91 ,  H01L27/10852

    摘要： A capacitor for a dynamic semiconductor memory cell, a memory and method of making a memory is disclosed. In one embodiment, a storage electrode of the capacitor has a pad-shaped lower section and a cup-shaped upper section, which is placed on top of the lower section. A lower section of a backside electrode encloses the pad-shaped section of the storage electrode. An upper section of the backside electrode is enclosed by the cup-shaped upper section of the storage electrode. A first capacitor dielectric separates the lower sections of the backside and the storage electrodes. A second capacitor dielectric separates the upper sections of the backside and the storage electrodes. The electrode area of the capacitor is enlarged while the requirements for the deposition of the capacitor dielectric are relaxed. Aspect ratios for deposition and etching processes are reduced.

    摘要翻译： 公开了用于动态半导体存储器单元的电容器，存储器和制造存储器的方法。 在一个实施例中，电容器的存储电极具有衬垫形下部和杯形上部，其放置在下部的顶部。 背面电极的下部包围存储电极的垫状部分。 背面电极的上部被储存电极的杯状上部包围。 第一电容器介质分离背面的下部和存储电极。 第二电容器电介质将背面的上部和存储电极分开。 电容器的电极面积被放大，而电容器电介质沉积的要求被放宽。 降低沉积和蚀刻工艺的长宽比。

    METHODS FOR FORMING AN INTEGRATED CIRCUIT, INCLUDING OPENINGS IN A MOLD LAYER
    9.
    发明申请
    METHODS FOR FORMING AN INTEGRATED CIRCUIT, INCLUDING OPENINGS IN A MOLD LAYER 有权
    形成集成电路的方法，包括模具层中的开口

    公开(公告)号：US20070286945A1

    公开(公告)日：2007-12-13

    申请号：US11687426

    申请日：2007-03-16

    申请人： Peter Lahnor ,  Odo Wunnicke ,  Johannes Heitmann ,  Peter Moll ,  Andreas Orth

    发明人： Peter Lahnor ,  Odo Wunnicke ,  Johannes Heitmann ,  Peter Moll ,  Andreas Orth

    IPC分类号： B05D5/12 ,  B05D5/00

    CPC分类号： H01L28/40 ,  H01L27/10861 ,  Y10S977/70 ,  Y10S977/72

    摘要： A method for forming an integrated circuit having openings in a mold layer and for producing capacitors is disclosed. In one embodiment, nanotubes or nanowires are grown vertically on a horizontal substrate surface. The nanotubes or nanowires serve as a template for forming openings in a mold layer. The substrate is covered with a mold material after the formation of the nanowires or nanotubes. One embodiment provides mold layers having openings with a much higher aspect ratio.

    摘要翻译： 公开了一种在模具层中形成具有开口并用于制造电容器的集成电路的方法。 在一个实施例中，纳米管或纳米线在水平衬底表面上垂直生长。 纳米管或纳米线用作在模具层中形成开口的模板。 在形成纳米线或纳米管之后，用模具材料覆盖基底。 一个实施例提供了具有高得多的纵横比的开口的模具层。