METHOD FOR FORMING SELF-ALIGNED OVERLAY MARK
    1.
    发明申请
    METHOD FOR FORMING SELF-ALIGNED OVERLAY MARK 有权
    用于形成自对准的覆盖标记的方法

    公开(公告)号:US20130210213A1

    公开(公告)日:2013-08-15

    申请号:US13372515

    申请日:2012-02-14

    IPC分类号: H01L21/311

    CPC分类号: G03F7/70633

    摘要: A method for forming a self-aligned overlay mark is disclosed. First, a first region, a second region and a main feature which is disposed between the first region and the second region all disposed on the substrate are provided. The first region defines a first edge and the second region defines a second edge. Second, a cut mask layer is formed to respectively cover the first region and the second region to expose the main feature. Next, the cut mask layer is determined if it is self-aligned with the second edge or the first edge, and creates a self-aligned overlay mark. Later, a main feature etching step is carried out to transfer the main feature into the substrate when the cut mask layer is determined to be self-aligned with the second edge or the first edge.

    摘要翻译: 公开了一种形成自对准覆盖标记的方法。 首先,设置设置在基板上的第一区域和第二区域之间的第一区域,第二区域和主要特征。 第一区域限定第一边缘,第二区域限定第二边缘。 第二,形成切割掩模层以分别覆盖第一区域和第二区域以暴露主要特征。 接下来,确定切割掩模层是否与第二边缘或第一边缘自对准,并且产生自对准覆盖标记。 然后,当切割掩模层被确定为与第二边缘或第一边缘自对准时,执行主要特征蚀刻步骤以将主要特征传递到基底中。

    Method for forming self-aligned overlay mark
    2.
    发明授权
    Method for forming self-aligned overlay mark 有权
    形成自对准重叠标记的方法

    公开(公告)号:US08664077B2

    公开(公告)日:2014-03-04

    申请号:US13372515

    申请日:2012-02-14

    IPC分类号: H01L21/76

    CPC分类号: G03F7/70633

    摘要: A method for forming a self-aligned overlay mark is disclosed. First, a first region, a second region and a main feature which is disposed between the first region and the second region all disposed on the substrate are provided. The first region defines a first edge and the second region defines a second edge. Second, a cut mask layer is formed to respectively cover the first region and the second region to expose the main feature. Next, the cut mask layer is determined if it is self-aligned with the second edge or the first edge, and creates a self-aligned overlay mark. Later, a main feature etching step is carried out to transfer the main feature into the substrate when the cut mask layer is determined to be self-aligned with the second edge or the first edge.

    摘要翻译: 公开了一种形成自对准覆盖标记的方法。 首先,设置设置在基板上的第一区域和第二区域之间的第一区域,第二区域和主要特征。 第一区域限定第一边缘,第二区域限定第二边缘。 第二,形成切割掩模层以分别覆盖第一区域和第二区域以暴露主要特征。 接下来,确定切割掩模层是否与第二边缘或第一边缘自对准,并且产生自对准覆盖标记。 然后,当切割掩模层被确定为与第二边缘或第一边缘自对准时,执行主要特征蚀刻步骤以将主要特征传递到基底中。

    Convulsive seizure detection and notification system
    4.
    发明授权
    Convulsive seizure detection and notification system 失效
    惊厥发作检测和通知系统

    公开(公告)号:US08779918B2

    公开(公告)日:2014-07-15

    申请号:US13328233

    申请日:2011-12-16

    申请人: Richard Housley

    发明人: Richard Housley

    IPC分类号: G08B1/08

    摘要: A convulsive seizure detection and notification device includes an acceleration module to measure acceleration of a body part of a user and generate acceleration measurement values, a storage to store a first threshold value and a second threshold value, and a data processor to compare acceleration measurement data with the first and second threshold values and generate a signal if a predetermined relationship between the acceleration measurement data and the first and second threshold values is satisfied.

    摘要翻译: 惊厥发作检测和通知装置包括:加速度模块,用于测量用户的身体部位的加速度并产生加速度测量值;存储器,用于存储第一阈值和第二阈值;以及数据处理器,用于比较加速度测量数据 如果满足加速度测量数据和第一和第二阈值之间的预定关系,则产生第一和第二阈值并产生信号。

    Methods Of Forming An Array Of Memory Cells, Methods Of Forming A Plurality Of Field Effect Transistors, Methods Of Forming Source/Drain Regions And Isolation Trenches, And Methods Of Forming A Series Of Spaced Trenches Into A Substrate
    5.
    发明申请
    Methods Of Forming An Array Of Memory Cells, Methods Of Forming A Plurality Of Field Effect Transistors, Methods Of Forming Source/Drain Regions And Isolation Trenches, And Methods Of Forming A Series Of Spaced Trenches Into A Substrate 有权
    形成记忆单元阵列的方法,形成多个场效应晶体管的方法,形成源极/漏极区域的方法和隔离沟槽以及将一系列间距沟槽形成基板的方法

    公开(公告)号:US20120021573A1

    公开(公告)日:2012-01-26

    申请号:US13248791

    申请日:2011-09-29

    IPC分类号: H01L21/8234 H01L21/302

    摘要: A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed.

    摘要翻译: 将一系列间隔开的沟槽形成到衬底中的方法包括在衬底上形成多个间隔开的线。 各向异性蚀刻的侧壁间隔物形成在间隔开的线的相对侧上。 这些线的个体具有比在紧邻线之间的紧邻的间隔物之间​​的最小宽度的最大宽度。 去除间隔的线以在间隔件之间形成一系列交替的第一和第二掩模开口。 第一掩模开口位于间隔开的线的位置并且比第二掩模开口更宽。 交替的第一和第二沟槽分别通过交替的第一和第二掩模开口同时蚀刻到衬底中,以形成比第二沟槽在衬底内更宽和更深的第一沟槽。 公开了其他实现和实施例。

    ANTI SPACER PROCESS AND SEMICONDUCTOR STRUCTURE GENERATED BY THE ANTI SPACER PROCESS
    6.
    发明申请
    ANTI SPACER PROCESS AND SEMICONDUCTOR STRUCTURE GENERATED BY THE ANTI SPACER PROCESS 审中-公开
    抗间歇过程产生的抗间隔过程和半导体结构

    公开(公告)号:US20140054756A1

    公开(公告)日:2014-02-27

    申请号:US13593503

    申请日:2012-08-23

    IPC分类号: H01L21/31 H01L29/02

    CPC分类号: H01L21/0273 H01L21/0271

    摘要: An anti spacer process, which comprises: (a) providing a resist layer including a non-uniform shape; (b) coating a target layer above the resist layer; (c) providing anti spacer trenches (spa) between the target layer and the resist layer; and (d) connecting at least part of the anti spacer trenches (spa) together to isolate a first part of the target layer and a second part of the target layer.

    摘要翻译: 一种防间隔法,其包括:(a)提供包含不均匀形状的抗蚀剂层; (b)在抗蚀剂层上涂覆目标层; (c)在目标层和抗蚀剂层之间提供抗间隔沟槽(spa); 和(d)将至少一部分抗间隔沟槽(温室)连接在一起,以隔离目标层的第一部分和目标层的第二部分。

    Methods Of Forming An Array Of Memory Cells, Methods Of Forming A Plurality Of Field Effect Transistors, Methods Of Forming Source/Drain Regions And Isolation Trenches, And Methods Of Forming A Series Of Spaced Trenches Into A Substrate
    7.
    发明申请
    Methods Of Forming An Array Of Memory Cells, Methods Of Forming A Plurality Of Field Effect Transistors, Methods Of Forming Source/Drain Regions And Isolation Trenches, And Methods Of Forming A Series Of Spaced Trenches Into A Substrate 有权
    形成记忆体阵列的方法,形成多个场效应晶体管的方法,形成源极/漏极区域的方法和隔离沟槽以及将一系列间距沟槽形成基板的方法

    公开(公告)号:US20130005115A1

    公开(公告)日:2013-01-03

    申请号:US13611517

    申请日:2012-09-12

    IPC分类号: H01L21/762 H01L21/308

    摘要: A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed.

    摘要翻译: 将一系列间隔开的沟槽形成到衬底中的方法包括在衬底上形成多个间隔开的线。 各向异性蚀刻的侧壁间隔物形成在间隔开的线的相对侧上。 这些线的个体具有比在紧邻线之间的紧邻的间隔物之间​​的最小宽度的最大宽度。 去除间隔的线以在间隔件之间形成一系列交替的第一和第二掩模开口。 第一掩模开口位于间隔开的线的位置并且比第二掩模开口更宽。 交替的第一和第二沟槽分别通过交替的第一和第二掩模开口同时蚀刻到衬底中,以形成比第二沟槽在衬底内更宽和更深的第一沟槽。 公开了其他实现和实施例。

    Pitch-halving integrated circuit process and integrated circuit structure made thereby
    8.
    发明授权
    Pitch-halving integrated circuit process and integrated circuit structure made thereby 有权
    由此产生的间距半导体集成电路工艺和集成电路结构

    公开(公告)号:US09245844B2

    公开(公告)日:2016-01-26

    申请号:US13845038

    申请日:2013-03-17

    摘要: A pitch-halving IC process is described. Parallel base line patterns are formed over a substrate, each being connected with a hammerhead pattern at a first or second side of the base line patterns, wherein the hammerhead patterns are arranged at the first side and the second side alternately, and the hammerhead patterns at the first or second side are arranged in a staggered manner. The above patterns are trimmed. A spacer is formed on the sidewalls of each base line pattern and the corresponding hammerhead pattern, including a pair of derivative line patterns, a loop pattern around the hammerhead pattern, and a turning pattern at the other end of the base line pattern. The base line patterns and the hammerhead patterns are removed. A portion of each loop pattern and at least a portion of each turning pattern are removed to disconnect each pair of derivative line patterns.

    摘要翻译: 描述了一个节距减半的IC过程。 平行的基线图形形成在基板上,每个基板在基线图案的第一或第二侧与锤头图案相连,其中锤头图案交替地布置在第一侧和第二侧,并且锤头图案 第一或第二侧以交错的方式布置。 上述图案被修剪。 在每个基线图案的侧壁和相应的锤头图案上形成间隔物,其包括一对衍生线图案,围绕锤头图案的环形图案,以及在基线图案的另一端的转动图案。 基线图案和锤头图案被去除。 去除每个环形图案的一部分和每个转动图案的至少一部分以断开每对衍生线图案。

    PITCH-HALVING INTEGRATED CIRCUIT PROCESS AND INTEGRATED CIRCUIT STRUCTURE MADE THEREBY
    9.
    发明申请
    PITCH-HALVING INTEGRATED CIRCUIT PROCESS AND INTEGRATED CIRCUIT STRUCTURE MADE THEREBY 有权
    PITCH-HALVING集成电路工艺和集成电路结构

    公开(公告)号:US20140264893A1

    公开(公告)日:2014-09-18

    申请号:US13845038

    申请日:2013-03-17

    IPC分类号: H01L21/768 H01L23/528

    摘要: A pitch-halving IC process is described. Parallel base line patterns are formed over a substrate, each being connected with a hammerhead pattern at a first or second side of the base line patterns, wherein the hammerhead patterns are arranged at the first side and the second side alternately, and the hammerhead patterns at the first or second side are arranged in a staggered manner. The above patterns are trimmed. A spacer is formed on the sidewalls of each base line pattern and the corresponding hammerhead pattern, including a pair of derivative line patterns, a loop pattern around the hammerhead pattern, and a turning pattern at the other end of the base line pattern. The base line patterns and the hammerhead patterns are removed. A portion of each loop pattern and at least a portion of each turning pattern are removed to disconnect each pair of derivative line patterns.

    摘要翻译: 描述了一个节距减半的IC过程。 平行的基线图形形成在基板上,每个基板在基线图案的第一或第二侧与锤头图案相连,其中锤头图案交替地布置在第一侧和第二侧,并且锤头图案 第一或第二侧以交错的方式布置。 上述图案被修剪。 在每个基线图案的侧壁和相应的锤头图案上形成间隔物,其包括一对衍生线图案,围绕锤头图案的环形图案,以及在基线图案的另一端的转动图案。 基线图案和锤头图案被去除。 去除每个环形图案的一部分和每个转动图案的至少一部分以断开每对衍生线图案。

    CONVULSIVE SEIZURE DETECTION AND NOTIFICATION SYSTEM
    10.
    发明申请
    CONVULSIVE SEIZURE DETECTION AND NOTIFICATION SYSTEM 失效
    有针对性的检测和通报系统

    公开(公告)号:US20130154827A1

    公开(公告)日:2013-06-20

    申请号:US13328233

    申请日:2011-12-16

    申请人: Richard Housley

    发明人: Richard Housley

    摘要: A convulsive seizure detection and notification device includes an acceleration module to measure acceleration of a body part of a user and generate acceleration measurement values, a storage to store a first threshold value and a second threshold value, and a data processor to compare acceleration measurement data with the first and second threshold values and generate a signal if a predetermine relationship between the acceleration measurement data and the first and second threshold values is satisfied.

    摘要翻译: 惊厥发作检测和通知装置包括:加速度模块,用于测量用户的身体部位的加速度并产生加速度测量值;存储器,用于存储第一阈值和第二阈值;以及数据处理器,用于比较加速度测量数据 具有第一和第二阈值,并且如果加速度测量数据与第一和第二阈值之间的预定关系被满足,则产生信号。