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1.发明申请WORD LINE VOLTAGE BOOST SYSTEM AND METHOD FOR NON-VOLATILE MEMORY DEVICES AND MEMORY DEVICES AND PROCESSOR-BASED SYSTEM USING SAME 有权用于非易失性存储器件和存储器件的WORD线电压升压系统和方法以及使用其的基于处理器的系统公开(公告)号：US20110170359A1
公开(公告)日：2011-07-14
申请号：US13070121
申请日：2011-03-23
IPC分类号： G11C16/10
摘要： The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array.
摘要翻译： 所选择的字线的电压通过从相邻字线电容耦合到所选字线的电压而增加到相应的串驱动晶体管能够驱动字线的电压。 在将编程电压施加到所选字线的串驱动晶体管之后，并且在将串驱动器电压施加到所有字的栅极之后，通过增加相邻字线的电压来将电压电容耦合到所选择的字线 的阵列驱动晶体管。
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公开(公告)号：US06584035B2
公开(公告)日：2003-06-24
申请号：US10032375
申请日：2001-12-21
IPC分类号： G11C800
CPC分类号： G11C16/08 , G11C7/1048 , G11C8/10 , G11C2207/002
摘要： Column select circuits having improved immunity to supply potential noise during sensing of the programmed state of a target memory cell are suited for use in low-voltage memory devices. Such column select circuits contain driver circuits having a filtered path and an unfiltered path for applying a supply potential to a gate of a pass transistor. The unfiltered path is utilized during a first sensing phase, such as during decoding or precharging of the bit lines, when transition speed of the pass transistors is desired. The filtered path is utilized at least during a second sensing phase while the sensing device is detecting the programmed state of the target memory cell. By reducing the noise of the supply potential using the filtered path, margins are improved on the sensing device and the sensing device is thus capable of operating at lower supply potentials.
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公开(公告)号：US08395939B2
公开(公告)日：2013-03-12
申请号：US13090754
申请日：2011-04-20
IPC分类号： G11C11/34
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/26 , G11C29/76 , G11C29/789 , G11C29/82 , G11C2211/5621 , G11C2211/5642
摘要： In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation.
摘要翻译： 在所公开的一个或多个实施例中，读取操作被补偿以用于背面图案效果。 通过偏置字线的读取操作产生位线电流。 作为背景图案效果测量阶段的一部分，在预定的时间间隔，将位线的放电状态的指示存储在耦合到每个位线的一组N个锁存器的锁存器中。 在测量阶段结束时，锁存器组包含一个多位字，它是该特定串行存储单元所经历的反向图案效应的指示。 这种背面图案效果指示用于随后的读取操作以调整操作的时间。
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公开(公告)号：US08233329B2
公开(公告)日：2012-07-31
申请号：US12365589
申请日：2009-02-04
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译： 例如，公开了存储器，存储器件和系统的编程方法。 在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。 在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。
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公开(公告)号：US08174897B2
公开(公告)日：2012-05-08
申请号：US13170420
申请日：2011-06-28
IPC分类号： G11C11/34
CPC分类号： G11C16/3454
摘要： Methods for programming a memory device and memory devices are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude.
摘要翻译： 提供了用于编程存储器件和存储器件的方法。 根据至少一种这样的方法，通过一系列编程脉冲对所选存储单元进行编程。 一系列编程脉冲被配置为编程脉冲，其中每组具有相同的脉冲量，并且组中的每个编程脉冲具有基本上相同的幅度（即编程电压）。 后续组的编程脉冲的幅度通过来自先前振幅的阶跃电压而增加。
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公开(公告)号：US20100157685A1
公开(公告)日：2010-06-24
申请号：US12477314
申请日：2009-06-03
IPC分类号： G11C16/04
CPC分类号： G11C16/3454
摘要： Methods for programming a memory device, memory devices, and a memory systems are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude.
摘要翻译： 提供了用于编程存储器件，存储器件和存储器系统的方法。 根据至少一种这样的方法，通过一系列编程脉冲对所选存储单元进行编程。 一系列编程脉冲被配置为编程脉冲，其中每组具有相同的脉冲量，并且组中的每个编程脉冲具有基本上相同的幅度（即编程电压）。 后续组的编程脉冲的幅度通过来自先前振幅的阶跃电压而增加。
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公开(公告)号：US20090290426A1
公开(公告)日：2009-11-26
申请号：US12123765
申请日：2008-05-20
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.
摘要翻译： 在编程存储器单元的选定字线时，在对所选字线的一页进行编程之后执行第一程序验证或读取操作，以便确定已被编程到预定参考点的第一数量的存储器单元 在编程的第一页分发。 在对所选字线的第二页进行编程之前，执行第二程序验证或读取操作以确定仍在参考点的第二数量的单元。 第一和第二数量之间的差异表示经历快速电荷损失的电池数量。 该差异用于在编程第二页之后确定用于第二页验证操作的调整电压。
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公开(公告)号：US20080285341A1
公开(公告)日：2008-11-20
申请号：US12038704
申请日：2008-02-27
CPC分类号： G11C16/3418
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes receiving a request to read data stored in a first cell of a first word line, performing a read operation on an adjacent cell of a second word line in response to the request, determining whether the first cell is in a disturbed condition based on the read operation. The method includes reading data stored in the first cell in response to the read request by applying a read reference voltage to the first word line and adjusting a sensing parameter if the first cell is in the disturbed condition.
摘要翻译： 本公开的实施例提供用于读取非易失性多电平存储器单元的方法，设备，模块和系统。 一种方法包括接收读取存储在第一字线的第一单元中的数据的请求，响应于该请求对第二字线的相邻单元执行读取操作，确定第一单元是否处于基于干扰状态 对读操作。 该方法包括：如果第一单元处于干扰状态，则通过将读取参考电压施加到第一字线并调整感测参数来读取响应于读取请求而存储在第一单元中的数据。
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公开(公告)号：US08917553B2
公开(公告)日：2014-12-23
申请号：US13072478
申请日：2011-03-25
CPC分类号： G11C16/34 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3459
摘要： Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying a signal to a line associated with a memory cell, the signal being generated based on digital information. The method can also include, while the signal is applied to the line, determining whether a state of the memory cell is near a target state when the digital information has a first value, and determining whether the state of the memory cell has reached the target state when the digital information has a second value. Other embodiments including additional memory devices and methods are described.
摘要翻译： 一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。 一种这样的方法可以包括将信号施加到与存储器单元相关联的线，该信号是基于数字信息生成的。 该方法还可以包括当信号被施加到线路时，当数字信息具有第一值时，确定存储器单元的状态是否接近目标状态，并且确定存储器单元的状态是否已经达到目标 当数字信息具有第二值时状态。 描述包括附加存储器件和方法的其它实施例。
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10.发明授权Word line voltage boost system and method for non-volatile memory devices and memory devices and processor-based system using same 有权用于非易失性存储器件和存储器件的字线升压系统和方法以及使用它的基于处理器的系统公开(公告)号：US08681559B2
公开(公告)日：2014-03-25
申请号：US13070121
申请日：2011-03-23
IPC分类号： G11C16/04
摘要： The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array.
摘要翻译： 所选择的字线的电压通过从相邻字线电容耦合到所选字线的电压而增加到相应的串驱动晶体管能够驱动字线的电压。 在将编程电压施加到所选字线的串驱动晶体管之后，并且在将串驱动器电压施加到所有字的栅极之后，通过增加相邻字线的电压来将电压电容耦合到所选择的字线 的阵列驱动晶体管。
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