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13 条记录 (耗时 0.019 秒)

    Memory cell with reduced soft error rate
    3.
    发明授权
    Memory cell with reduced soft error rate 有权
    具有降低的软错误率的存储单元

    公开(公告)号：US07214990B1

    公开(公告)日：2007-05-08

    申请号：US11063704

    申请日：2005-02-22

    申请人： Shih-Ked Lee ,  Chuen-Der Lien ,  Louis Huang ,  Gaolong Jin ,  Wanqing Cao ,  Guo-Qiang Lo

    发明人： Shih-Ked Lee ,  Chuen-Der Lien ,  Louis Huang ,  Gaolong Jin ,  Wanqing Cao ,  Guo-Qiang Lo

    IPC分类号： H01L27/11

    CPC分类号： H01L28/24 ,  H01L27/016 ,  H01L27/0802 ,  H01L29/78

    摘要： The present invention includes SRAM memory cells and methods for forming SRAM cells having reduced soft error rate. The SRAM cell includes a first NMOS transistor and a first PMOS transistor having a common gate, and a second NMOS transistor and a second PMOS transistor having a common gate. A first resistor is electrically coupled on one end to the drains of the first PMOS transistor and the first NMOS transistor; and is electrically coupled on the other end to the common gate of the second NMOS and second PMOS transistors. A second resistor is electrically coupled on one end to the drains of the second PMOS transistor and the second NMOS transistor; and is electrically coupled on the other end to the common gate of the first NMOS transistor and the first PMOS transistor. The added resistor can be embedded in a contact opening such that it does not take up valuable surface area on the semiconductor substrate. Thereby, data loss from soft errors can be avoided while preserving small memory cell size.

    摘要翻译： 本发明包括SRAM存储单元和用于形成具有降低的软错误率的SRAM单元的方法。 SRAM单元包括第一NMOS晶体管和具有公共栅极的第一PMOS晶体管，以及具有公共栅极的第二NMOS晶体管和第二PMOS晶体管。 第一电阻器的一端电耦合到第一PMOS晶体管和第一NMOS晶体管的漏极; 并且在另一端电耦合到第二NMOS和第二PMOS晶体管的公共栅极。 第二电阻器的一端电耦合到第二PMOS晶体管和第二NMOS晶体管的漏极; 并且在另一端电耦合到第一NMOS晶体管和第一PMOS晶体管的公共栅极。 添加的电阻器可以嵌入在接触开口中，使得其不占据半导体衬底上的有价值的表面积。 因此，可以避免从软错误的数据丢失，同时保持小的存储单元尺寸。

    Multi-step tungsten etchback process to preserve barrier integrity in an integrated circuit structure
    5.
    发明授权
    Multi-step tungsten etchback process to preserve barrier integrity in an integrated circuit structure 有权
    多步钨回蚀工艺，以保护集成电路结构中的屏障完整性

    公开(公告)号：US06872668B1

    公开(公告)日：2005-03-29

    申请号：US09671667

    申请日：2000-09-26

    申请人： Wanqing Cao ,  Guo-Qiang Lo ,  Shih-Ked Lee ,  Hongyong Xue

    发明人： Wanqing Cao ,  Guo-Qiang Lo ,  Shih-Ked Lee ,  Hongyong Xue

    IPC分类号： C23F4/00 ,  H01L21/302 ,  H01L21/321 ,  H01L21/3213

    CPC分类号： H01L21/32136 ,  C23F4/00 ,  H01L21/32115

    摘要： An improved method is provided for etching back a tungsten layer that overlies a titanium nitride adhesion layer on a semiconductor structure. This method includes the steps of: (1) performing a first plasma etchback of the tungsten layer for a first predetermined time period, such that a thin layer of tungsten remains over the adhesion layer at the end of the first plasma etchback, (2) actively or passively cooling the resulting semiconductor structure to a temperature of 35° C. or lower, and then (3) performing a second plasma etchback of the tungsten layer until an endpoint is detected, thereby exposing the adhesion layer. Cooling the semiconductor structure prior to the second plasma etchback ensures that the titanium nitride adhesion layer is at a relatively low temperature during the second plasma etchback. The titanium nitride adhesion layer etches significantly slower at lower temperatures, thereby making it easier to stop the second plasma etchback on the adhesion layer.

    摘要翻译： 提供了一种改进的方法来蚀刻覆盖半导体结构上的氮化钛粘合层的钨层。 该方法包括以下步骤：（1）在第一预定时间段内执行钨层的第一等离子体回蚀，使得在第一等离子体回蚀结束时，薄层的钨保留在粘附层上方，（2） 主动地或被动地将所得半导体结构冷却至35℃或更低的温度，然后（3）执行钨层的第二等离子体回蚀，直到检测到端点，从而暴露粘附层。 在第二等离子体回蚀之前冷却半导体结构确保在第二等离子体回蚀期间氮化钛粘合层处于相对较低的温度。 氮化钛粘附层在较低温度下蚀刻显着更慢，从而使得更容易停止粘附层上的第二等离子体回蚀。

    Cobalt silicide structure for improving gate oxide integrity and method for fabricating same
    7.
    发明授权
    Cobalt silicide structure for improving gate oxide integrity and method for fabricating same 失效
    用于提高栅极氧化物完整性的硅化钴结构及其制造方法

    公开(公告)号：US06281102B1

    公开(公告)日：2001-08-28

    申请号：US09484580

    申请日：2000-01-13

    申请人： Wanqing Cao ,  Sang-Yun Lee ,  Guo-Qiang Lo ,  Shih-Ked Lee

    发明人： Wanqing Cao ,  Sang-Yun Lee ,  Guo-Qiang Lo ,  Shih-Ked Lee

    IPC分类号： H01L213205

    CPC分类号： H01L29/665 ,  H01L21/28518

    摘要： An improved method is provided for fabricating a cobalt silicide structure that includes the steps of: (1) forming a silicon structure, wherein a native oxide is located over a first surface of the silicon structure, (2) loading the silicon structure into a chamber, (3) introducing a vacuum to the chamber, (4) depositing a titanium layer over the first surface of the silicon structure, wherein the thickness of the titanium layer is selected to remove substantially all of the native oxide, (5) depositing a cobalt layer over the titanium layer, (6) depositing an oxygen impervious cap layer over the cobalt layer; and then (7) breaking the vacuum in the chamber, and (8) subjecting the silicon structure, the titanium layer, the cobalt layer and the cap layer to an anneal, thereby forming the cobalt silicide structure. The cap layer can be, for example, titanium or titanium nitride. The resulting cobalt silicide structure is substantially free from oxygen (i.e., oxide). Consequently, an underlying gate oxide or substrate is advantageously protected from the effects of cobalt silicide spiking.

    摘要翻译： 提供了一种用于制造钴硅化物结构的改进方法，其包括以下步骤：（1）形成硅结构，其中自然氧化物位于硅结构的第一表面上，（2）将硅结构加载到室中 （3）向腔室引入真空，（4）在硅结构的第一表面上沉积钛层，其中选择钛层的厚度以去除基本上所有的天然氧化物，（5）沉积 钴层，（6）在钴层上沉积不透氧的盖层; 然后（7）破坏腔室中的真空，（8）对硅结构，钛层，钴层和盖层进行退火，从而形成钴硅化物结构。 盖层可以是例如钛或氮化钛。 所得的钴硅化物结构基本上不含氧（即氧化物）。 因此，有利地保护下面的栅极氧化物或衬底免受硅化钴尖峰的影响。

    Method of forming particles using a supercritical fluid
    8.
    发明授权
    Method of forming particles using a supercritical fluid 失效
    使用超临界流体形成颗粒的方法

    公开(公告)号：US5864923A

    公开(公告)日：1999-02-02

    申请号：US920287

    申请日：1997-08-26

    申请人： Stephane Fabrice Rouanet ,  William Edward McGovern ,  Wanqing Cao ,  John M. Moses ,  Angel L. Carrillo ,  Irving M. Klotz

    发明人： Stephane Fabrice Rouanet ,  William Edward McGovern ,  Wanqing Cao ,  John M. Moses ,  Angel L. Carrillo ,  Irving M. Klotz

    IPC分类号： A61K8/00 ,  A61K8/02 ,  A61K8/20 ,  A61K8/23 ,  A61K8/26 ,  A61K8/27 ,  A61K8/28 ,  A61K8/33 ,  A61K8/36 ,  A61K8/49 ,  A61Q15/00 ,  B01D9/00 ,  B01J2/00 ,  B01J13/00 ,  C01F7/00 ,  C01F7/48 ,  C01F7/56 ,  C01G25/00 ,  B01D17/00 ,  C07C7/10

    CPC分类号： A61Q15/00 ,  A61K8/042 ,  A61K8/26 ,  B01J13/0091

    摘要： A method for providing aerogels, and aerogels produced according to the method, is described. As one aspect, antiperspirant compounds that are in aerogel form, and antiperspirant and deodorant compositions including such salts, are described. The method involves contacting a solution containing material to be processed with a species selected to precipitate the material and selected so as to be miscible with the solvent system of the solution. After the material is precipitated, the material may be washed with the precipitating species until it is substantially free of solvent system. Then, the precipitating species containing the material precipitate is taken above its critical point, and the supercritical fluid is exhausted above its critical temperature. Alternately, a separate isolating species is introduced to displace the precipitating species, or the precipitating species/solvent system mixture. The isolating species then is taken above its critical point, and exhausted above its critical temperature. The invention provides for batch or continuous processes.

    摘要翻译： 描述了一种提供气凝胶和根据该方法生产的气凝胶的方法。 一方面，描述了气凝胶形式的止汗化合物，以及包含这些盐的止汗剂和除臭剂组合物。 该方法包括将待处理材料的溶液与选择的物质接触以沉淀材料并选择以便与溶液的溶剂体系混溶。 材料沉淀后，材料可以用沉淀物质洗涤，直到其基本上不含溶剂体系。 然后，将含有物质沉淀物的沉淀物质高于其临界点，超临界流体在其临界温度以上耗尽。 或者，引入单独的隔离物质以置换沉淀物质或沉淀物质/溶剂体系混合物。 然后将隔离物质置于其临界点以上，并在其临界温度以上耗尽。 本发明提供批量或连续方法。

    Thin film resistor structure
    9.
    发明授权
    Thin film resistor structure 有权
    薄膜电阻器结构

    公开(公告)号：US07400026B2

    公开(公告)日：2008-07-15

    申请号：US11342134

    申请日：2006-01-26

    申请人： Gaolong Jin ,  Wanqing Cao ,  Guo-Qiang Lo ,  Shih-Ked Lee

    发明人： Gaolong Jin ,  Wanqing Cao ,  Guo-Qiang Lo ,  Shih-Ked Lee

    IPC分类号： H01L29/00

    CPC分类号： H01L28/24 ,  H01L27/016 ,  H01L27/0802 ,  H01L29/78

    摘要： The present invention relates to a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a conductive layer of the gate structure. A layer of titanium nitride is deposited and a rapid thermal anneal is performed in an oxygen ambient. The rapid thermal anneal incorporates oxygen into the titanium nitride, forming titanium oxynitride film. A layer of dielectric material is then deposited and etched-back to form a dielectric plug that fills the remaining portion of the via. The titanium oxynitride film is patterned to form a titanium oxynitride structure that is electrically coupled to the gate structure.

    摘要翻译： 本发明涉及形成在半导体衬底上的薄膜电阻器。 形成栅极结构，并且在栅极结构上形成介电层。 然后蚀刻通孔，其延伸穿过电介质层，以暴露栅极结构的导电层。 沉积一层氮化钛，并在氧气氛中进行快速热退火。 快速热退火将氧气纳入氮化钛中，形成氮氧化钛膜。 然后沉积介电材料层并将其蚀刻回来形成填充通孔的剩余部分的电介质塞子。 将氮氧化钛膜图案化以形成电耦合到栅极结构的氮氧化钛结构。

    Method for forming a thin film resistor structure
    10.
    发明授权
    Method for forming a thin film resistor structure 失效
    用于形成薄膜电阻器结构的方法

    公开(公告)号：US07078306B1

    公开(公告)日：2006-07-18

    申请号：US10805718

    申请日：2004-03-22

    申请人： Gaolong Jin ,  Wanqing Cao ,  Guo-Qiang Lo ,  Shih-Ked Lee

    发明人： Gaolong Jin ,  Wanqing Cao ,  Guo-Qiang Lo ,  Shih-Ked Lee

    IPC分类号： H01L21/20

    CPC分类号： H01L28/24 ,  H01L27/016 ,  H01L27/0802 ,  H01L29/78

    摘要： The present invention relates to a method for forming a thin film resistor and a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a portion of the gate structure. A layer of titanium nitride is deposited using a chemical vapor deposition process. A rapid thermal anneal is performed in an oxygen ambient. The rapid thermal anneal incorporates oxygen into the titanium nitride, forming titanium oxynitride film. A layer of dielectric material is then deposited and etched-back to form a dielectric plug that fills the remaining portion of the via. The titanium oxynitride film is patterned to form a titanium oxynitride structure that is electrically coupled to the gate structure. A metal layer is deposited and patterned to form an interconnect structure that electrically couples the titanium oxynitride structure to other circuitry.

    摘要翻译： 本发明涉及形成在半导体衬底上的薄膜电阻器和薄膜电阻器的形成方法。 形成栅极结构，并且在栅极结构上形成介电层。 然后蚀刻通孔，其延伸穿过电介质层，以暴露栅极结构的一部分。 使用化学气相沉积工艺沉积一层氮化钛。 在氧环境中进行快速热退火。 快速热退火将氧气纳入氮化钛中，形成氮氧化钛膜。 然后沉积介电材料层并将其蚀刻回来形成填充通孔的剩余部分的电介质塞子。 将氮氧化钛膜图案化以形成电耦合到栅极结构的氮氧化钛结构。 金属层被沉积​​并图案化以形成将氮氧化钛结构电耦合到其它电路的互连结构。