利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

10 条记录 (耗时 0.099 秒)

    WIDEBAND BEAM FORMING DEVICE; WIDEBAND BEAM STEERING DEVICE AND CORRESPONDING METHODS
    2.
    发明申请
    WIDEBAND BEAM FORMING DEVICE; WIDEBAND BEAM STEERING DEVICE AND CORRESPONDING METHODS 有权
    宽带光束形成装置; 宽带光束转向装置及相应方法

    公开(公告)号：US20130002488A1

    公开(公告)日：2013-01-03

    申请号：US13494549

    申请日：2012-06-12

    申请人： Qi WANG ,  Richard Stirling-Gallacher ,  Ralf Boehnke

    发明人： Qi WANG ,  Richard Stirling-Gallacher ,  Ralf Boehnke

    IPC分类号： H01Q3/00

    CPC分类号： H01Q3/22 ,  G01S13/0209 ,  G01S13/26 ,  G01S13/34 ,  G01S13/887 ,  G01S13/89

    摘要： A beam forming device and method as well as to a beam steering device and method are described. The imaging beam forming device comprises a wideband transmit unit comprising at least one transmit antenna, a receiver unit comprising at least two receive antennas and at least one receive element that receive radiation from said scene and that generate receive signals from said received radiation, and a beam forming unit that performs beam forming to form a receive beam and obtain beam formed output signals from said receive signals by use of beam forming weights. For different samples or groups of subsequent samples of a receive signal, a sample representing said receive signal at a different frequency, a frequency-dependent weight is used for beam forming, which frequency-dependent weights are adapted to result in a predetermined shape of said receive beam.

    摘要翻译： 描述了波束形成装置和方法以及波束转向装置和方法。 成像光束形成装置包括宽带发射单元，其包括至少一个发射天线，包括至少两个接收天线的接收机单元和接收来自所述场景的辐射并且从所述接收到的辐射产生接收信号的至少一个接收元件，以及 波束形成单元，其执行波束形成以形成接收波束，并且通过使用波束形成权重从所述接收信号获得波束形成的输出信号。 对于接收信号的后续样本的不同样本或组，以不同频率表示所述接收信号的样本，频率依赖权重用于波束形成，所述频率依赖权重适于导致所述接收信号的预定形状 接收光束。

    BEAM FORMING DEVICE AND METHOD USING FREQUENCY-DEPENDENT CALIBRATION
    3.
    发明申请
    BEAM FORMING DEVICE AND METHOD USING FREQUENCY-DEPENDENT CALIBRATION 审中-公开
    光束形成装置和使用频率相关校准的方法

    公开(公告)号：US20130016003A1

    公开(公告)日：2013-01-17

    申请号：US13546625

    申请日：2012-07-11

    申请人： Richard STIRLING-GALLACHER ,  Miquel TESTAR ,  Furkan DAYI ,  Ralf BOEHNKE ,  Marcel BLECH ,  Qi WANG

    发明人： Richard STIRLING-GALLACHER ,  Miquel TESTAR ,  Furkan DAYI ,  Ralf BOEHNKE ,  Marcel BLECH ,  Qi WANG

    IPC分类号： H01Q3/26 ,  G01S7/40

    CPC分类号： G01S7/4026 ,  G01S7/35 ,  G01S13/343 ,  G01S13/89 ,  G01S2007/403 ,  G01S2007/4034 ,  G01S2013/0245 ,  H01Q3/26 ,  H01Q3/267

    摘要： A beam forming device that enables the use for wideband digital beam forming and provide a high accuracy a beam forming device comprises a transmitter arrangement and a receiver arrangement, wherein the total number of transmit antennas and receive antennas is at least three. A beam forming unit performs beam forming to obtain beam formed output signals from said receive signals by use of corrected beam forming weights. A correction unit corrects preliminary beam forming weights in amplitude and/or phase by use of frequency-dependent final calibration coefficients representing the different amplitude and/or phase responses of the different channels between said at least one transmit antenna and said at least one receive antenna at two or more separate frequencies covered by the radiation transmitted towards the scene.

    摘要翻译： 能够用于宽带数字波束形成并提供高精度的波束形成装置的波束形成装置包括发射器装置和接收器装置，其中发射天线和接收天线的总数至少为三个。 波束形成单元通过使用校正的波束形成权重来执行波束形成以从所述接收信号获得波束形成的输出信号。 校正单元通过使用代表在所述至少一个发射天线与所述至少一个接收天线之间的不同信道的不同幅度和/或相位响应的依赖于频率的最终校准系数来校正振幅和/或相位中的初步波束形成权重 在由朝向场景传播的辐射覆盖的两个或更多个分开的频率处。

    QUADRATURE DIVIDER
    4.
    发明申请
    QUADRATURE DIVIDER 有权
    四分法师

    公开(公告)号：US20160285436A1

    公开(公告)日：2016-09-29

    申请号：US14127954

    申请日：2013-09-18

    申请人： Mark L. NEIDENGARD ,  Qi WANG

    发明人： Mark L. NEIDENGARD ,  Qi WANG

    IPC分类号： H03K3/037

    CPC分类号： H03K3/037 ,  H03K5/15 ,  H03K23/588

    摘要： Described is an apparatus of a quadrature divider. The apparatus is independent of a jam latch, and is for generating a quadrature clock. The apparatus comprises: a first selection unit controllable by a clock signal, the first selection unit to directly or indirectly generate a first phase of the quadrature clock; a third selection unit controllable by the clock signal, the third selection unit to receive the first phase of the quadrature clock, the third selection unit to directly or indirectly generate a third phase of the quadrature clock, wherein the first selection unit to receive the third phase of the quadrature clock.

    摘要翻译： 描述了正交分频器的装置。 该装置独立于卡锁锁存器，并且用于产生正交时钟。 该装置包括：由时钟信号控制的第一选择单元，第一选择单元直接或间接产生正交时钟的第一相位; 由所述时钟信号控制的第三选择单元，所述第三选择单元接收所述正交时钟的所述第一相位，所述第三选择单元直接或间接产生所述正交时钟的第三相位，其中所述第一选择单元接收所述第三选择单元， 正交时钟的相位。

    STORAGE METHOD, STORAGE SYSTEM, AND CONTROLLER
    5.
    发明申请
    STORAGE METHOD, STORAGE SYSTEM, AND CONTROLLER 有权
    存储方法，存储系统和控制器

    公开(公告)号：US20110264833A1

    公开(公告)日：2011-10-27

    申请号：US13168552

    申请日：2011-06-24

    申请人： Wei ZHANG ,  Xianhong LV ,  Qi WANG ,  Ruiqi FAN

    发明人： Wei ZHANG ,  Xianhong LV ,  Qi WANG ,  Ruiqi FAN

    IPC分类号： G06F13/14

    CPC分类号： G06F3/0658 ,  G06F3/0626 ,  G06F3/0671

    摘要： A storage method, a storage system, and a controller are disclosed. The method is applicable to a system that includes at least one controller, at least two Peripheral Component Interconnection Express (PCIE) Input/Output (IO) modules, and at least two storage devices. The at least two storage devices are connected through a PCIE switch chip of the at least one controller, and the at least two PCIE IO modules are connected through a PCIE switch chip of the at least one controller. The method includes: receiving a request message from a server through the at least two PCIE IO modules; and accessing the at least two storage devices according to the request message. The at least two PCIE IO modules are shared between controllers, thereby saving resources; and the storage devices access the controllers without the need of a hard disk controller or a hard disk extension chip, thereby saving costs.

    摘要翻译： 公开了存储方法，存储系统和控制器。 该方法适用于包括至少一个控制器，至少两个外围组件互连Express（PCIE）输入/输出（IO）模块）和至少两个存储设备的系统。 所述至少两个存储设备通过所述至少一个控制器的PCIE交换芯片连接，并且所述至少两个PCIE IO模块通过所述至少一个控制器的PCIE交换芯片连接。 该方法包括：通过至少两个PCIE IO模块从服务器接收请求消息; 以及根据所述请求消息访问所述至少两个存储设备。 至少两个PCIE IO模块在控制器之间共享，从而节省资源; 并且存储设备访问控制器而不需要硬盘控制器或硬盘扩展芯片，从而节省成本。

    RECEIVING APPARATUS AND METHOD FOR RECEIVING SIGNALS IN A WIRELESS COMMUNICATION SYSTEM WITH IMPROVED EQUALIZATION PERFORMANCE
    6.
    发明申请
    RECEIVING APPARATUS AND METHOD FOR RECEIVING SIGNALS IN A WIRELESS COMMUNICATION SYSTEM WITH IMPROVED EQUALIZATION PERFORMANCE 有权
    接收设备和在无线通信系统中接收信号的方法，具有改进的均衡性能

    公开(公告)号：US20100135376A1

    公开(公告)日：2010-06-03

    申请号：US12620797

    申请日：2009-11-18

    申请人： Zhaocheng WANG ,  Qi WANG

    发明人： Zhaocheng WANG ,  Qi WANG

    IPC分类号： H04L27/08 ,  H03H7/40 ,  H04B1/10

    CPC分类号： H04L27/01 ,  H04L25/022 ,  H04L25/0224 ,  H04L25/03159

    摘要： The present invention relates to a receiving apparatus (11) for receiving signals in a wireless communication system, in which the signals comprise a dedicated channel estimation sequence, comprising a gain control means (3) adapted to control the gain of a received signal, a channel estimation means (8) adapted to perform a channel estimation on the basis of a dedicated channel estimation sequence comprised in a received signal, a gain error correction means (12) adapted to correct a gain error in the result of said channel estimation caused by said gain control means (3) on the basis of said dedicated channel estimation sequence comprised in the received signal, and an equalizing means (7) adapted to perform an equalization on the received signal on the basis of the gain corrected channel estimation result. The present invention further relates to a corresponding receiving method.

    摘要翻译： 本发明涉及一种用于在无线通信系统中接收信号的接收装置（11），其中信号包括专用信道估计序列，包括适于控制接收信号的增益的增益控制装置（3） 信道估计装置（8），其适于基于包括在接收信号中的专用信道估计序列执行信道估计;增益误差校正装置（12），适于校正所述信道估计的结果中的增益误差，所述增益误差由 所述增益控制装置（3）基于包含在所述接收信号中的所述专用信道估计序列，以及均衡装置（7），其适于基于所述增益校正信道估计结果对接收信号执行均衡。 本发明还涉及相应的接收方法。

    NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION
    8.
    发明申请
    NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION 有权
    非易失性存储器件及其相关操作方法

    公开(公告)号：US20080055964A1

    公开(公告)日：2008-03-06

    申请号：US11850130

    申请日：2007-09-05

    申请人： Sang-beom KANG ,  Yong-jin YOON ,  Qi WANG

    发明人： Sang-beom KANG ,  Yong-jin YOON ,  Qi WANG

    IPC分类号： G11C7/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/009

    摘要： A nonvolatile memory device comprises a first voltage generation unit, a second voltage generation unit, a first circuit block, and a discharge unit. The first voltage generation unit generates a first voltage with a first magnitude. The second voltage generation unit generates a second voltage with a second magnitude greater than the first magnitude. The first circuit block selectively receives the first voltage or the second voltage through an input node. The discharge unit discharges the input node between a time point where the input node has been charged with the second voltage and a time point where the input node receives the first voltage.

    摘要翻译： 非易失性存储器件包括第一电压产生单元，第二电压产生单元，第一电路块和放电单元。 第一电压产生单元产生具有第一量值的第一电压。 第二电压产生单元产生具有大于第一幅值的第二幅度的第二电压。 第一电路块通过输入节点选择性地接收第一电压或第二电压。 放电单元在输入节点已经被充电的时间点与第二电压之间和输入节点接收到第一电压的时间点之间对输入节点进行放电。

    VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM
    10.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM 有权
    可变电阻存储器件和系统

    公开(公告)号：US20090251954A1

    公开(公告)日：2009-10-08

    申请号：US12417679

    申请日：2009-04-03

    申请人： Qi WANG ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Taek-Sung KIM ,  Kwang-Ho KIM ,  Hyun-Ho CHOI

    发明人： Qi WANG ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Taek-Sung KIM ,  Kwang-Ho KIM ,  Hyun-Ho CHOI

    IPC分类号： G11C11/00 ,  G11C8/00 ,  G11C11/416

    CPC分类号： G11C16/08 ,  G11C8/12

    摘要： Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.

    摘要翻译： 公开了一种半导体存储器件，包括具有分成第一和第二区域的多个可变电阻存储器单元的存储单元阵列。 I / O电路被配置为在控制逻辑的控制下访问存储单元阵列，以响应于外部命令访问第一或第二区域。 I / O电路使用存储单元单元访问第一区域，并且使用页面单元访问第二区域。