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23 条记录 (耗时 0.021 秒)

    Diode with alterable conductivity and method of making same
    1.
    发明授权
    Diode with alterable conductivity and method of making same 失效
    具有可变导电性的二极管及其制造方法

    公开(公告)号：US06344679B1

    公开(公告)日：2002-02-05

    申请号：US09443524

    申请日：1999-11-19

    申请人： William A. Klaasen ,  Wilbur D. Pricer ,  Jed Hickory Rankin

    发明人： William A. Klaasen ,  Wilbur D. Pricer ,  Jed Hickory Rankin

    IPC分类号： G11C1706

    CPC分类号： H01L23/5258 ,  G11C17/06 ,  G11C17/16 ,  H01L23/5254 ,  H01L27/0814 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device (102) having a plurality of diodes (100) with alterable electrical conductivity by a source of energy (30), e.g., a laser, external to the semiconductor device. The diodes are formed and energy is applied to alter the electrical conductivity at least 10%, and preferably by several orders of magnitude. Certain embodiments (20, 40 and 50) are formed so as to function as anti-fuses, while another embodiment (60) functions as a fuse. The diodes may be formed as planar diodes (20, 40, 50 and 60) or as lateral diodes (70).

    摘要翻译： 一种具有多个二极管（100）的半导体器件（102），所述多个二极管（100）具有通过所述半导体器件外部的能量源（30）例如激光器具有可改变的导电性。 形成二极管并施加能量以改变至少10％的电导率，优选地几个数量级。 某些实施例（20,40和50）被形成为用作抗熔丝，而另一个实施例（60）用作保险丝。 二极管可以形成为平面二极管（20,40,50和60）或形成为侧向二极管（70）。

    Circuit for operating a control transistor from a fusible link
    3.
    发明授权
    Circuit for operating a control transistor from a fusible link 失效
    用于从可熔链路操作控制晶体管的电路

    公开(公告)号：US5999037A

    公开(公告)日：1999-12-07

    申请号：US904397

    申请日：1997-07-31

    申请人： Kerry Bernstein ,  Daniel C. Edelstein ,  William A. Klaasen ,  Wilbur D. Pricer

    发明人： Kerry Bernstein ,  Daniel C. Edelstein ,  William A. Klaasen ,  Wilbur D. Pricer

    IPC分类号： G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/785

    摘要： A circuit for enabling a controlled transistor in response to an ablated fusible link. The fusible link is configured so that no d.c. potential resides on the link once it has been ablated. A source of alternating voltage is capacitively coupled to the fusible link and maintains the fusible link from reconnection due to dendrite formation once it is ablated. An a.c. to d.c. voltage converter is used to signal the change in condition of the fusible link, thus, actuating a control transistor of a redundant circuit element in a replacement operation.

    摘要翻译： 一种用于响应于消融的可熔链路启用受控晶体管的电路。 熔丝链接被配置为没有直流 一旦消融，电位就位于链接上。 交流电压源电容耦合到可熔链路，并且一旦烧蚀就会由于枝晶形成而使可熔连接件重新连接。 一个 到达 电压转换器用于发信号通知熔断条件的变化，从而在更换操作中致动冗余电路元件的控制晶体管。

    Error correcting logic system
    5.
    发明授权
    Error correcting logic system 有权
    错误校正逻辑系统

    公开(公告)号：US07642813B2

    公开(公告)日：2010-01-05

    申请号：US11850857

    申请日：2007-09-06

    申请人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Philip G. Emma ,  John A. Fifield ,  Paul D. Kartschoke ,  William A. Klaasen ,  Norman J. Rohrer

    IPC分类号： H03K19/20 ,  H03K19/094 ,  H03K19/003

    CPC分类号： H03K19/007

    摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system.

    摘要翻译： 本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。 该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。 该系统适用于动态或静态逻辑系统。 该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。 此外，提供了在设计过程中使用的机器可读介质中体现的设计结构，并且包括这种纠错逻辑系统。

    System technique for detecting soft errors in statically coupled CMOS logic
    6.
    发明授权
    System technique for detecting soft errors in statically coupled CMOS logic 失效
    用于检测静态耦合CMOS逻辑中的软错误的系统技术

    公开(公告)号：US06453431B1

    公开(公告)日：2002-09-17

    申请号：US09346509

    申请日：1999-07-01

    申请人： Kerry Bernstein ,  Andres Bryant ,  William A. Klaasen ,  Wilbur David Pricer

    发明人： Kerry Bernstein ,  Andres Bryant ,  William A. Klaasen ,  Wilbur David Pricer

    IPC分类号： G06K504

    CPC分类号： G11C5/005 ,  G06F11/00

    摘要： Circuit for detecting error transients in logic circuits due to atomic events or other non-recurring noise sources includes a first circuit coupled to a data line for sensing a first signal on the data line at a first point in time (T1) and a second circuit coupled to the data line for sensing the first signal on the data line at a second point in time (T2) such that a time difference between T1 and T2 is small enough so that the first signal is still present on the data line in the absence of a perturbation event and such that the time difference between T1 and T2 is large enough so that any such perturbation event is resolved. A compare circuit coupled to the first and second circuits compares the sensing of the first signal by the first and second circuits, and generates an error signal in response to a non-compare.

    摘要翻译： 用于检测由于原子事件或其他非循环噪声源引起的逻辑电路中的错误瞬变的电路包括耦合到数据线的第一电路，用于感测在第一时间点（T1）的数据线上的第一信号，以及第二电路 耦合到数据线，用于在第二时间点（T2）感测数据线上的第一信号，使得T1和T2之间的时间差足够小，使得第一信号在不存在的情况下仍然存在于数据线上 的扰动事件，并且使得T1和T2之间的时间差足够大，使得任何这样的扰动事件被解决。 耦合到第一和第二电路的比较电路比较第一和第二电路对第一信号的感测，并且响应于非比较而产生误差信号。

    Radiation detecting system
    7.
    发明授权
    Radiation detecting system 失效
    辐射检测系统

    公开(公告)号：US06969859B2

    公开(公告)日：2005-11-29

    申请号：US10249872

    申请日：2003-05-14

    申请人： William A. Klaasen ,  Edward J. Nowak ,  Norman J. Rohrer

    发明人： William A. Klaasen ,  Edward J. Nowak ,  Norman J. Rohrer

    IPC分类号： G01T1/15 ,  G01T1/17 ,  G01T1/24

    CPC分类号： G01T1/17

    摘要： A radiation detecting system including a radiation detecting section having one or more radiation detecting circuits and a circuit adjustment section for adjusting other circuitry to be protected. Radiation detecting circuits are provided to detect a pulse of radiation and/or a total radiation dose accumulation.

    摘要翻译： 一种辐射检测系统，包括具有一个或多个辐射检测电路的辐射检测部分和用于调节要被保护的其它电路的电路调整部分。 提供辐射检测电路以检测辐射脉冲和/或总辐射剂量累积。

    Semiconductor chip structures with embedded thermal conductors and a thermal sink disposed over opposing substrate surfaces
    8.
    发明授权
    Semiconductor chip structures with embedded thermal conductors and a thermal sink disposed over opposing substrate surfaces 失效
    具有嵌入式热导体的半导体芯片结构和设置在相对基板表面上的散热器

    公开(公告)号：US06773952B2

    公开(公告)日：2004-08-10

    申请号：US10243397

    申请日：2002-09-12

    申请人： Douglas S. Armbrust ,  William F. Clark ,  William A. Klaasen ,  William T. Motsiff ,  Timothy D. Sullivan

    发明人： Douglas S. Armbrust ,  William F. Clark ,  William A. Klaasen ,  William T. Motsiff ,  Timothy D. Sullivan

    IPC分类号： H01L2100

    CPC分类号： H01L23/5222 ,  H01L23/3677 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/00

    摘要： Semiconductor chip structures are provided with embedded thermal conductors for removing heat from one or more electrically conductive circuit members thereof, wherein the circuit members are formed on one or more dielectric layers above a substrate, each layer having a low dielectric constant and a low thermal conductivity. One or more cooling posts, for example, multiple thermally conductive plugs, are selectively disposed within the semiconductor chip structure adjacent to one or more electrically conductive members and thermally coupled thereto so that heat produced by the members is transferred into and through the cooling posts for forwarding to the substrate and/or to an upper surface of the semiconductor chip structure. The backside of the substrate has a thermal sink thermally coupled thereto and electrically isolated from the substrate. The thermal sink includes one or more thermally conductive via structures embedded within the substrate and aligned to thermally contact to the cooling posts disposed above the substrate.

    摘要翻译： 半导体芯片结构设置有用于从一个或多个导电电路构件去除热量的嵌入式热导体，其中电路构件形成在衬底上方的一个或多个电介质层上，每层具有低介电常数和低热导率 。 一个或多个冷却柱，例如多个导热塞，被选择性地设置在半导体芯片结构内邻近一个或多个导电构件并与其热耦合，使得由构件产生的热量被传送到冷却柱中并通过冷却柱 转移到衬底和/或到半导体芯片结构的上表面。 衬底的背面具有热耦合到其上并与衬底电隔离的散热器。 散热器包括一个或多个热传导通孔结构，其嵌入衬底内并对准以与设置在衬底上方的冷却柱热接触。