公开(公告)号：US06743268B2

公开(公告)日：2004-06-01

申请号：US10051135

申请日：2002-01-18

申请人： William J. Cote ,  Daniel C. Edelstein ,  Naftali E. Lustig

发明人： William J. Cote ,  Daniel C. Edelstein ,  Naftali E. Lustig

IPC分类号： C09G102

CPC分类号： H01L21/76843 ,  C09G1/02 ,  C23F3/00 ,  H01L21/3212 ,  H01L21/7684

摘要： A tantalum-based liner for copper metallurgy is selectively removed by chemical-mechanical planarization (CMP) in an acidic slurry of an oxidizer such as hydrogen peroxide, deionized water, a corrosion inhibitor such as BTA, and a surfactant such as Duponol SP, resulting in a high removal rate of the liner without appreciable removal of the exposed copper and with minimal dishing.

摘要翻译： 通过化学机械平面化（CMP）在氧化剂如过氧化氢，去离子水，腐蚀抑制剂如BTA的酸性浆料和诸如Duponol SP的表面活性剂中选择性地除去用于铜冶金的钽基衬垫，得到 在较高的衬里去除速率下，无明显去除暴露的铜和最小的凹陷。

公开(公告)号：US06375693B1

公开(公告)日：2002-04-23

申请号：US09307123

申请日：1999-05-07

申请人： William J. Cote ,  Daniel C. Edelstein ,  Naftali E. Lustig

发明人： William J. Cote ,  Daniel C. Edelstein ,  Naftali E. Lustig

IPC分类号： C09K314

CPC分类号： H01L21/76843 ,  C09G1/02 ,  C23F3/00 ,  H01L21/3212 ,  H01L21/7684

摘要： A tantalum-based liner for copper metallurgy is selectively removed by chemical-mechanical planarization (CMP) in an acidic slurry of an oxidizer such as hydrogen peroxide, deionized water, a corrosion inhibitor such as BTA, and a surfactant such as DUPONOL SP, resulting in a high removal rate of the liner without appreciable removal of the exposed copper and with minimal dishing.

摘要翻译： 通过化学机械平面化（CMP）在氧化剂如过氧化氢，去离子水，腐蚀抑制剂如BTA的酸性浆料和诸如DUPONOL SP的表面活性剂中选择性除去用于铜冶金的钽基衬垫，得到 在较高的衬里去除速率下，无明显去除暴露的铜和最小的凹陷。

公开(公告)号：US6153043A

公开(公告)日：2000-11-28

申请号：US20010

申请日：1998-02-06

申请人： Daniel C. Edelstein ,  Wilma J. Horkans ,  Stephen E. Luce ,  Naftali E. Lustig ,  Keith R. Pope ,  Peter D. Roper

发明人： Daniel C. Edelstein ,  Wilma J. Horkans ,  Stephen E. Luce ,  Naftali E. Lustig ,  Keith R. Pope ,  Peter D. Roper

IPC分类号： H01L21/304 ,  B24B37/34 ,  B24B49/12 ,  H01L21/00 ,  H01L21/02 ,  H01L21/321 ,  C23F1/02

CPC分类号： B24B37/34 ,  B24B49/12 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/67028

摘要： Eliminating exposure of PN junctions to light capable of invoking a photovoltaic effect and/or inhibiting the oxidation and reduction reactions induced by the photovoltaic effect prevents the electrochemical dissolution of metal components on semiconductor devices by electrolysis. A darkened enclosure for use on tools for wafer CMP, brush cleaning, unloading, and rinsing will eliminate exposure. Alternatively, illumination of a semiconductor wafer can be limited to wavelengths of light that do not provide enough energy to induce a photovoltaic effect. An inhibitor in the CMP slurry and/or post-CMP water rinse blocks the oxidation and/or reduction reactions. A blocking agent, such as a high molecular weight surfactant, will interfere with both the oxidation and reduction reactions at the metal surface. Also, a poisoning agent will impede the reduction portion of electrolysis.

摘要翻译： 消除PN结对能够引起光伏效应的光和/或抑制由光电效应引起的氧化和还原反应的光的暴露防止金属组分通过电解电化学溶解在半导体器件上。 用于晶圆CMP，刷子清洁，卸载和冲洗的工具的变暗外壳将消除曝光。 或者，可以将半导体晶片的照明限制在不能提供足够能量以引起光伏效应的光的波长。 CMP浆料中的抑制剂和/或CMP后的水冲洗阻止氧化和/或还原反应。 封闭剂，例如高分子量表面活性剂，将干扰金属表面的氧化和还原反应。 此外，中毒剂会阻碍电解还原部分。

公开(公告)号：US20090075472A1

公开(公告)日：2009-03-19

申请号：US11857760

申请日：2007-09-19

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

摘要翻译： 提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。 等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。 以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽 用于形成线沟槽和通孔腔的离子蚀刻。 减少的线偏压对金属互连结构的电产量具有有益的影响。

公开(公告)号：US07030031B2

公开(公告)日：2006-04-18

申请号：US10604056

申请日：2003-06-24

申请人： William C. Wille ,  Daniel C. Edelstein ,  William J. Cote ,  Peter E. Biolsi ,  John Fritche ,  Allan W. Upham

发明人： William C. Wille ,  Daniel C. Edelstein ,  William J. Cote ,  Peter E. Biolsi ,  John Fritche ,  Allan W. Upham

IPC分类号： H01L21/302

CPC分类号： H01L21/76808 ,  H01L21/31144 ,  H01L21/76804

摘要： This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized. With this method, the problem of photoresist poisoning by the interlevel dielectric material is alleviated.

摘要翻译： 本发明涉及集成电路器件中的双镶嵌互连结构的制造。 具体地，公开了一种利用平面化材料和扩散阻挡材料在低k电介质薄膜中形成单一或双镶嵌结构的方法。 在该方法的优选双镶嵌实施例中，首先在电介质材料中形成通孔，然后将平坦化材料沉积在通孔和介电材料上，并且阻挡材料沉积在平坦化材料上。 然后在成像材料中光刻地形成沟槽，通过阻挡材料蚀刻成平坦化材料，并将沟槽图案转移到电介质材料。 在这些蚀刻步骤期间和之后，去除成像，阻挡层和平坦化材料。 然后可以将所得的双镶嵌结构金属化。 通过这种方法，可以减轻层间电介质材料的光致抗蚀剂中毒问题。

公开(公告)号：US08470706B2

公开(公告)日：2013-06-25

申请号：US13602119

申请日：2012-09-01

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

摘要翻译： 提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。 等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。 以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽 用于形成线沟槽和通孔腔的离子蚀刻。 减少的线偏压对金属互连结构的电产量具有有益的影响。

公开(公告)号：US20120329269A1

公开(公告)日：2012-12-27

申请号：US13602119

申请日：2012-09-01

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

摘要翻译： 提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。 等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。 以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽 用于形成线沟槽和通孔腔的离子蚀刻。 减少的线偏压对金属互连结构的电产量具有有益的影响。

公开(公告)号：US08481423B2

公开(公告)日：2013-07-09

申请号：US11857760

申请日：2007-09-19

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

公开(公告)号：US06649531B2

公开(公告)日：2003-11-18

申请号：US09994340

申请日：2001-11-26

申请人： William J. Cote ,  Timothy J. Dalton ,  Prakash Chimanlal Dev ,  Daniel C. Edelstein ,  Scott D. Halle ,  Gill Yong Lee ,  Arpan P. Mahorowala

发明人： William J. Cote ,  Timothy J. Dalton ,  Prakash Chimanlal Dev ,  Daniel C. Edelstein ,  Scott D. Halle ,  Gill Yong Lee ,  Arpan P. Mahorowala

IPC分类号： H01L21302

CPC分类号： H01L21/76808 ,  H01L21/31633

摘要： A process for forming a damascene structure includes depositing a bilayer comprising a first dielectric layer and a second dielectric layer onto a substrate, wherein the first layer has a dielectric constant higher than the second layer, and wherein the second layer is selected from a low k dielectric material comprising Si, C, O and H. The multi-step damascene structure is patterned into the dielectric bilayer using highly selective anisotropic reactive ion etching. Photoresist, polymers and post etch residues are removed from the substrate using a plasma ashing process without damaging the underlying dielectric layers.

摘要翻译： 用于形成镶嵌结构的方法包括将包括第一介电层和第二介电层的双层沉积到基板上，其中第一层具有高于第二层的介电常数，并且其中第二层选自低k 包含Si，C，O和H的介电材料。使用高选择性各向异性反应离子蚀刻，将多步镶嵌结构图案化成电介质双层。 使用等离子体灰化处理从基板去除光致抗蚀剂，聚合物和后蚀刻残留物，而不损坏下面的介电层。

公开(公告)号：US09245794B2

公开(公告)日：2016-01-26

申请号：US13614492

申请日：2012-09-13

申请人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Takeshi Nogami

发明人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Takeshi Nogami

IPC分类号： H05K1/09 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76846 ,  H01L21/76844 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

摘要： An interconnect structure including an alloy liner positioned directly between a diffusion barrier and a Cu alloy seed layer as well as methods for forming such an interconnect structure are provided. The alloy liner of the present invention is formed by thermally reacting a previously deposited diffusion barrier metal alloy layer with an overlying Cu alloy seed layer. During the thermal reaction, the metal alloys from the both the diffusion barrier and the Cu alloys seed layer react forming a metal alloy reaction product between the diffusion barrier and the Cu seed layer.

摘要翻译： 提供了包括直接位于扩散阻挡层和Cu合金种子层之间的合金衬垫的互连结构以及用于形成这种互连结构的方法。 本发明的合金衬垫通过使预先沉积的扩散阻挡金属合金层与覆盖的Cu合金种子层热反应形成。 在热反应期间，来自扩散阻挡层和Cu合金种子层的金属合金在扩散阻挡层和Cu籽晶层之间反应形成金属合金反应产物。