公开(公告)号：US07465882B2

公开(公告)日：2008-12-16

申请号：US11610082

申请日：2006-12-13

申请人： Wiren D. Becker ,  Zhaoqing Chen ,  George Katopis

发明人： Wiren D. Becker ,  Zhaoqing Chen ,  George Katopis

IPC分类号： H05K1/03

CPC分类号： H05K1/0224 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0219 ,  H05K1/0253 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/09681 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

摘要： Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines.

摘要翻译： 通过垂直通孔的信号线导体在用于支撑和互连集成电路芯片的绝缘基板中设置有连接相应电源和接地层的相邻过孔中的屏蔽导体。 通过使用以菱形图案布置的电源平面和接地平面导电网格，​​可以使屏蔽导体存在于信号通孔周围的位置。 电力平面和地平面网格具有彼此的左右镜像关系，并被置换以放置菱形的角部，以避免重叠任何网格线。

公开(公告)号：US20090108465A1

公开(公告)日：2009-04-30

申请号：US12259811

申请日：2008-10-28

申请人： Wiren D. Becker ,  Zhaoqing Chen ,  George Katopis

发明人： Wiren D. Becker ,  Zhaoqing Chen ,  George Katopis

IPC分类号： H01L23/52

CPC分类号： H05K1/0224 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0219 ,  H05K1/0253 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/09681 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

摘要： Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines.

公开(公告)号：US20080142257A1

公开(公告)日：2008-06-19

申请号：US11610082

申请日：2006-12-13

申请人： Wiren D. Becker ,  Zhaoqing Chen ,  George Katopis

发明人： Wiren D. Becker ,  Zhaoqing Chen ,  George Katopis

IPC分类号： H05K1/11 ,  H05K1/00 ,  H05K1/03

CPC分类号： H05K1/0224 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0219 ,  H05K1/0253 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/09681 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

摘要： Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines.

摘要翻译： 通过垂直通孔的信号线导体在用于支撑和互连集成电路芯片的绝缘基板中设置有连接相应电源和接地层的相邻过孔中的屏蔽导体。 通过使用以菱形图案布置的电源平面和接地平面导电网格，​​可以使屏蔽导体存在于信号通孔周围的位置。 电力平面和地平面网格具有彼此的左右镜像关系，并被置换以放置菱形的角部，以避免重叠任何网格线。

公开(公告)号：US07985927B2

公开(公告)日：2011-07-26

申请号：US12269082

申请日：2008-11-12

申请人： Wiren D. Becker ,  Zhaoqing Chen ,  George Katopis

发明人： Wiren D. Becker ,  Zhaoqing Chen ,  George Katopis

IPC分类号： H05K1/03

CPC分类号： H05K1/0224 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0219 ,  H05K1/0253 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/09681 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

摘要： Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines.

公开(公告)号：US07897879B2

公开(公告)日：2011-03-01

申请号：US12259811

申请日：2008-10-28

申请人： Wiren D. Becker ,  Zhaoqing Chen ,  George Katopis

发明人： Wiren D. Becker ,  Zhaoqing Chen ,  George Katopis

IPC分类号： H05K1/03

CPC分类号： H05K1/0224 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0219 ,  H05K1/0253 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/09681 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

摘要： Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines.

摘要翻译： 通过垂直通孔的信号线导体在用于支撑和互连集成电路芯片的绝缘基板中设置有连接相应电源和接地层的相邻过孔中的屏蔽导体。 通过使用以菱形图案布置的电源平面和接地平面导电网格，​​可以使屏蔽导体存在于信号通孔周围的位置。 电力平面和地平面网格具有彼此的左右镜像关系，并被置换以放置菱形的角部，以避免重叠任何网格线。

公开(公告)号：US20090113703A1

公开(公告)日：2009-05-07

申请号：US12269082

申请日：2008-11-12

申请人： Wiren D. Becker ,  Zhaoqing Chen ,  George Katopis

发明人： Wiren D. Becker ,  Zhaoqing Chen ,  George Katopis

IPC分类号： H05K3/10

CPC分类号： H05K1/0224 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0219 ,  H05K1/0253 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/09681 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

摘要： Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines.

摘要翻译： 通过垂直通孔的信号线导体在用于支撑和互连集成电路芯片的绝缘基板中设置有连接相应电源和接地层的相邻过孔中的屏蔽导体。 通过使用以菱形图案布置的电源平面和接地平面导电网格，​​可以使屏蔽导体存在于信号通孔周围的位置。 电力平面和地平面网格具有彼此的左右镜像关系，并被置换以放置菱形的角部，以避免重叠任何网格线。

公开(公告)号：US07355125B2

公开(公告)日：2008-04-08

申请号：US11281688

申请日：2005-11-17

申请人： Wiren D. Becker ,  Bruce J. Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

发明人： Wiren D. Becker ,  Bruce J. Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

IPC分类号： H05K1/03

CPC分类号： H05K1/0262 ,  H05K1/0298 ,  H05K1/141 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09663

摘要： The present invention relates to computer hardware design and in particular to a printed circuit board comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In order to provide a printed circuit board having an improved signal return path for basically all relevant signal layers at transitions between card, connector, module and chip while still holding the cross-section structure simple, it is proposed to establish a layer structure whereina) a split voltage plane is located adjacent to one side of one of said reference planes and comprises conducting portions for all of said at least three different voltage levels in respective plane parts, andb) a signal layer being located adjacent to said reference planes.

摘要翻译： 本发明涉及计算机硬件设计，特别是涉及一种印刷电路板，其中印刷电路板包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板部件的布线。 为了提供一种印刷电路板，其具有改进的信号返回路径，用于基本上在卡，连接器，模块和芯片之间的转变处的所有相关信号层，同时仍然保持横截面结构简单，因此建议建立层结构，其中 ）分裂电压平面位于所述参考平面中的一个的一侧附近，并且包括用于各平面部分中的所有所述至少三个不同电压电平的导电部分，以及b）位于所述参考平面附近的信号层。

公开(公告)号：US07742315B2

公开(公告)日：2010-06-22

申请号：US11282041

申请日：2005-11-17

申请人： Wiren D. Becker ,  Bruce J. Chamberlin ,  Gerald J. Fahr ,  Roland Frech ,  Dierk Kaller ,  George Katopis ,  Erich Klink ,  Thomas-Michael Winkel

发明人： Wiren D. Becker ,  Bruce J. Chamberlin ,  Gerald J. Fahr ,  Roland Frech ,  Dierk Kaller ,  George Katopis ,  Erich Klink ,  Thomas-Michael Winkel

IPC分类号： H05K1/11 ,  H05K1/14

CPC分类号： H05K1/11 ,  H01R12/523 ,  H01R13/6466 ,  H01R13/6471 ,  H01R13/6589 ,  H01R13/6625 ,  H05K1/0216 ,  H05K1/162 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/10189

摘要： The present invention relates to computer hardware design, and in particular to a printed circuit board (card) comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In particular at locations, where the pins of a card-to-card connector enter the layer structure of the card discontinuities brake the high frequency signal return path of a given signal wiring.In order to close the signal return path around a signal path from card to card including the connector, and thus to limit the signal coupling while concurrently keeping the card design as simple as possible, it is proposed to provide a) an additional capacitance for a given signal wiring in a discontinuity section, b) wherein the additional capacitance is formed by a voltage island placed within a signal layer located next to the given signal wiring.

摘要翻译： 本发明涉及计算机硬件设计，特别涉及一种包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板组件的布线的印刷电路板（卡）。 特别是在卡到卡连接器的引脚进入卡不连续的层结构的位置处，制动给定信号布线的高频信号返回路径。 为了封闭从包括连接器的卡到卡的信号路径周围的信号返回路径，并且因此限制信号耦合，同时保持卡设计尽可能简单，建议提供a）附加电容 在不连续部分中的给定信号布线，b）其中附加电容由放置在位于给定信号布线旁边的信号层内的电压岛形成。

公开(公告)号：US20070109726A1

公开(公告)日：2007-05-17

申请号：US11281688

申请日：2005-11-17

申请人： Wiren Becker ,  Bruce Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

发明人： Wiren Becker ,  Bruce Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

IPC分类号： H02B1/00

CPC分类号： H05K1/0262 ,  H05K1/0298 ,  H05K1/141 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09663

摘要： The present invention relates to computer hardware design and in particular to a printed circuit board comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In order to provide a printed circuit board having an improved signal return path for basically all relevant signal layers at transitions between card, connector, module and chip while still holding the cross-section structure simple, it is proposed to establish a layer structure wherein a) a split voltage plane is located adjacent to one side of one of said reference planes and comprises conducting portions for all of said at least three different voltage levels in respective plane parts, and b) a signal layer being located adjacent to said reference planes.

摘要翻译： 本发明涉及计算机硬件设计，特别是涉及一种印刷电路板，其中印刷电路板包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板部件的布线。 为了提供一种印刷电路板，其具有改进的信号返回路径，用于基本上在卡，连接器，模块和芯片之间的转变处的所有相关信号层，同时仍然保持横截面结构简单，因此建议建立层结构，其中 ）分裂电压平面位于所述参考平面中的一个的一侧附近，并且包括用于各个平面部分中的所有所述至少三个不同电压电平的导电部分，以及b）位于所述参考平面附近的信号层。

公开(公告)号：US20050127500A1

公开(公告)日：2005-06-16

申请号：US10732015

申请日：2003-12-10

申请人： Evan Colgan ,  Claudis Feger ,  Gary Goth ,  George Katopis ,  John Magerlein ,  Edmund Sprogis

发明人： Evan Colgan ,  Claudis Feger ,  Gary Goth ,  George Katopis ,  John Magerlein ,  Edmund Sprogis

IPC分类号： H01L23/34 ,  H01L21/50 ,  H01L21/56 ,  H01L23/10 ,  H01L23/12 ,  H01L23/36 ,  H01L23/367 ,  H01L23/373

CPC分类号： H01L23/367 ,  H01L23/3737 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： In an integrated circuit packaging structure, such as in an MCM or in a SCM, a compliant thermally conductive material is applied between a heat-generating integrated circuit chip and a substrate attached thereto. Raised regions are defined on the back side of the chip aligned to areas of a higher than average power density on the front active surface of the chip such that a thinner layer of the compliant thermally conductive material is disposed between the chip and the substrate in this area after assembly thereof resulting in a reduced “hot-spot” temperature on the chip. In an exemplary embodiment, the substrate includes one of a heat sink, cooling plate, thermal spreader, heat pipe, thermal hat, package lid, or other cooling member.

摘要翻译： 在诸如在MCM或SCM中的集成电路封装结构中，在发热集成电路芯片和附着于其之间的衬底之间施加兼容的导热材料。 凸起区域被限定在芯片的背面上，与芯片的前活性表面上的高于平均功率密度的区域相对准，使得在该芯片和衬底之间设置较薄的柔性导热材料层 组装后的区域导致芯片上的“热点”温度降低。 在示例性实施例中，基板包括散热器，冷却板，散热器，热管，散热帽，封装盖或其它冷却构件中的一个。