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    Method of making a double injection field effect transistor
    1.
    发明授权
    Method of making a double injection field effect transistor 失效
    制造双注入场效应晶体管的方法

    公开(公告)号：US4882295A

    公开(公告)日：1989-11-21

    申请号：US328666

    申请日：1989-03-27

    申请人： Wolodymyr Czubatyj ,  Michael G. Hack ,  Michael Shur

    发明人： Wolodymyr Czubatyj ,  Michael G. Hack ,  Michael Shur

    IPC分类号： H01L27/092 ,  H01L29/739 ,  H01L29/772 ,  H01L29/812 ,  H01L33/00 ,  H01L33/18 ,  H01S5/042 ,  H01S5/062 ,  H01S5/30

    CPC分类号： H01L33/18 ,  H01L27/0928 ,  H01L29/739 ,  H01L29/7722 ,  H01L29/8122 ,  H01L33/0041 ,  H01S5/0422 ,  H01S5/30 ,  H01S5/06203 ,  Y10S148/105

    摘要： Double injection field effect transistors, which may be horizontally or vertically arranged, each include a body of semiconductor material extending between two current-carrying electrodes and forming a current path therebetween. The semiconductor body of each may be substantially intrinsic or lightly doped. One or more control electrodes or gates located adjacent to each current path project a variable electric field over the ambipolar path, which modulates current by controlling the amount of charge carriers of both polarities injected into the semiconductor body. In most of the single gate embodiments, the electrodes extend across a portion, preferably a major portion such as 75% or 90%, or the length of the current path, but not the entire length of the current path. The embodiments having a plurality of gates typically have two insulated gates, one extending from the anode electrode and the other extending from the cathode electrode. The gates in a single device may overlap.Embodiments having electrodes with doped microcrystalline regions for improved carrier injection are disclosed. Methods for making planar double injection field effect transistors having a plurality of deposited noncrystalline semiconductor layers for clean interface formation between semiconductor layers are also disclosed.

    摘要翻译： 可以水平或垂直布置的双注入场效应晶体管每个包括在两个载流电极之间延伸并在其间形成电流路径的半导体材料体。 每个半导体本体可以是基本上固有的或轻掺杂的。 位于每个电流路径附近的一个或多个控制电极或门在双极路径上投射可变电场，该双极路径通过控制注入到半导体主体中的两极性的电荷载流子的量来调制电流。 在大多数单栅极实施例中，电极延伸穿过一部分，优选地主要部分，例如75％或90％，或电流路径的长度，但不延伸到当前路径的整个长度。 具有多个栅极的实施例通常具有两个绝缘栅极，一个从阳极电极延伸，另一个从阴极延伸。 单个设备中的门可能重叠。 公开了具有用于改进载流子注入的具有掺杂微晶区域的电极的实施例。 还公开了用于制造具有用于半导体层之间的清洁界面形成的多个沉积的非晶半导体层的平面双注入场效应晶体管的方法。

    Array having multiple channel structures with continuously doped interchannel regions
    2.
    发明授权
    Array having multiple channel structures with continuously doped interchannel regions 失效
    阵列具有具有连续掺杂的通道间区域的多个通道结构

    公开(公告)号：US5703382A

    公开(公告)日：1997-12-30

    申请号：US559862

    申请日：1995-11-20

    申请人： Michael G. Hack ,  I-Wei Wu

    发明人： Michael G. Hack ,  I-Wei Wu

    IPC分类号： G02F1/1368 ,  H01L27/12 ,  H01L29/786 ,  A01L29/04 ,  G02F1/1343

    CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L29/78645 ,  G02F1/1368

    摘要： Cell circuitry in an array on a substrate includes a TFT or other structure with a series of two or more channels and with an intrachannel region between each pair of adjacent channels in the series. Each intrachannel region has a continuously distribution of dopant particles and the distribution of dopant particles in the intrachannel regions together controls reverse gate bias leakage current without significantly reducing ON current. The average dopant density in intrachannel regions can be sufficiently low to ensure that reverse gate bias leakage current is approximately constant across a range of reverse gate bias voltages. For applications such as light valve arrays, sensor arrays, and memory arrays in which each cell includes a capacitive element for storing a level of charge in one of two or more voltage bands, the average dopant density of intrachannel regions can ensure that reverse gate bias leakage current is sufficiently low that a level of charge stored by the capacitive element remains within its voltage band during a storage period.

    摘要翻译： 衬底中的阵列中的单元电路包括具有一系列两个或更多个通道的TFT或其它结构，并且在串联中的每对相邻通道之间具有通道内区域。 每个通道内区域具有掺杂剂颗粒的连续分布，并且通道区域中的掺杂剂颗粒的分布一起控制反向栅极偏置泄漏电流，而不显着降低导通电流。 沟道内区域中的平均掺杂剂密度可以足够低以确保反向栅极偏置漏电流在反向栅极偏置电压的范围内近似恒定。 对于诸如光阀阵列，传感器阵列和存储器阵列的应用，其中每个单元包括用于在两个或更多个电压带之一中存储电荷水平的电容元件，通道间区域的平均掺杂剂密度可以确保反向栅极偏置 泄漏电流足够低，使得在存储周期期间由电容元件存储的电荷水平保持在其电压带内。

    Array with amorphous silicon TFTs in which channel leads overlap insulating region no more than maximum overlap
    4.
    发明授权
    Array with amorphous silicon TFTs in which channel leads overlap insulating region no more than maximum overlap 失效
    具有非晶硅TFT的阵列，其中沟道引线重叠绝缘区不超过最大重叠

    公开(公告)号：US5717223A

    公开(公告)日：1998-02-10

    申请号：US578780

    申请日：1995-12-22

    申请人： Michael G. Hack ,  Rene A. Lujan

    发明人： Michael G. Hack ,  Rene A. Lujan

    IPC分类号： G02F1/136 ,  G02F1/1368 ,  H01L21/336 ,  H01L27/12 ,  H01L29/786 ,  H01L29/04

    CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L29/66765 ,  G02F1/1368 ,  H01L29/78618 ,  H01L29/78669

    摘要： An array includes cells, each with a bottom gate amorphous silicon thin film transistor (a-Si TFT). Each a-Si TFT has an undoped amorphous silicon layer over its gate region and extending beyond its edges. Each a-Si TFT also has an insulating region with edges approximately aligned with the edges of its gate region. Two channel leads of doped semiconductor material such as microcrystalline silicon or polycrystalline silicon are on the undoped amorphous silicon layer, each overlapping an edge of the insulating region by a distance that is no more than a maximum overlap distance, which in turn is no more than 1.0 .mu.m.

    摘要翻译： 阵列包括具有底栅非晶硅薄膜晶体管（a-Si TFT）的单元。 每个a-Si TFT在其栅极区域上具有未掺杂的非晶硅层并且延伸超过其边缘。 每个a-Si TFT还具有绝缘区域，其边缘与其栅极区域的边缘大致对准。 掺杂半导体材料如微晶硅或多晶硅的两通道引线位于未掺杂的非晶硅层上，每个引线与绝缘区域的边缘重叠不超过最大重叠距离的距离，其不超过 1.0亩

    Reducing leakage current in a thin-film transistor with charge carrier densities that vary in two dimensions
    5.
    发明授权
    Reducing leakage current in a thin-film transistor with charge carrier densities that vary in two dimensions 失效
    减小电荷载流子密度在两维中变化的薄膜晶体管中的漏电流

    公开(公告)号：US5401982A

    公开(公告)日：1995-03-28

    申请号：US205974

    申请日：1994-03-03

    申请人： Tsu-Jae King ,  Michael G. Hack

    发明人： Tsu-Jae King ,  Michael G. Hack

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/786 ,  H01L29/78

    CPC分类号： H01L29/78696 ,  H01L29/66757 ,  H01L29/78609 ,  H01L29/78621 ,  H01L2029/7863

    摘要： In the channel layer of a thin film transistor (TFT), a channel and its drain meet at a transition within a transition region. The channel extends in a first, or horizontal, dimension away from the drain and extends in a second, or vertical, dimension from a side away from the gate to a side toward the gate. The charge carrier densities in the transition region vary in the second dimension in a way that reduces leakage current, because the position of the maximum electric field is moved away from the gate and its magnitude is reduced. Variation of densities in the second dimension can be produced by high angle implantation of a dopant and a counterdopant, providing a transition region between the drain and the channel underneath the gate. Variation of densities in the second dimension can also be produced with non-angled implantation by a process in which a sidewall spacer offsets the drain, providing a transition region that is between the drain and the channel and that can be doped independently of the drain. In a symmetric TFT in which either channel lead can function as a drain, charge carrier densities can vary in the second dimension at the transitions between each channel lead and the channel.

    摘要翻译： 在薄膜晶体管（TFT）的沟道层中，沟道及其漏极在过渡区域内的过渡处相遇。 该通道在远离排水口的第一或水平尺寸上延伸，并且从第二或垂直尺寸的一侧向远离浇口的一侧延伸到一侧朝向浇口。 过渡区域中的电荷载流子密度在第二维度上以减少泄漏电流的方式变化，因为最大电场的位置移动离开栅极并且其幅度减小。 可以通过掺杂剂和反掺杂剂的高角度注入来产生第二维度中的密度变化，从而在栅极下方的漏极和沟道之间提供过渡区域。 第二维度中的密度的变化也可以通过其中侧壁间隔件抵消漏极的过程以非倾斜注入产生，提供位于漏极和沟道之间的过渡区域，并且可以独立于漏极掺杂。 在其中任一通道引线可用作漏极的对称TFT中，电荷载流子密度可以在每个通道引线和通道之间的转换处在第二维度上变化。

    Fabricating fully self-aligned amorphous silicon device
    8.
    发明授权
    Fabricating fully self-aligned amorphous silicon device 失效
    制造完全自对准非晶硅器件

    公开(公告)号：US5733804A

    公开(公告)日：1998-03-31

    申请号：US577634

    申请日：1995-12-22

    申请人： Michael G. Hack ,  Rene A. Lujan

    发明人： Michael G. Hack ,  Rene A. Lujan

    IPC分类号： H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L29/786

    CPC分类号： H01L29/78696 ,  H01L27/1214 ,  H01L29/66765 ,  Y10S438/949

    摘要： An amorphous silicon thin film transistor (a-Si TFT) or other a-Si device is produced by depositing and lithographically patterning a layer of doped semiconductor material such as microcrystalline or polycrystalline silicon to produce a conductive lead. The semiconductor material is deposited over an insulating region and over an exposed part of an amorphous silicon layer. The insulating region has an edge that is over and approximately aligned with an edge of a gate region. The doped semiconductor layer therefore forms a junction to the amorphous silicon layer at the edge of the insulating region, approximately aligned with the edge of the gate region. Self-aligned lithographic patterning is performed in such a way that the conductive lead overlaps the insulating region by a distance that is no more than a maximum overlap distance. The maximum overlap distance can, for example, be no more than 1.0 .mu.m, and can be 0.5 .mu.m. The insulating region and the doped semiconductor layer can both be lithographically patterned by a combination of self-aligned backside exposure and top masked exposure. Overlap distance can be controlled by timing backside exposure, application of developer, baking, or application of etchant.

    摘要翻译： 通过对诸如微晶或多晶硅的掺杂半导体材料的层进行沉积和光刻图案来制造非晶硅薄膜晶体管（a-Si TFT）或其它a-Si器件，以产生导电引线。 半导体材料沉积在非晶硅层的绝缘区域和暴露部分之上。 绝缘区域具有在栅极区域的边缘上方且大致对齐的边缘。 因此，掺杂半导体层在绝缘区域的边缘处形成大致与栅极区域的边缘对准的非晶硅层的结。 以这样的方式进行自对准平版印刷图案，使得导电引线与绝缘区域重叠不超过最大重叠距离的距离。 最大重叠距离例如可以不大于1.0μm，并且可以是0.5μm。 绝缘区域和掺杂半导体层可以通过自对准背面曝光和顶部掩模曝光的组合进行光刻图案化。 重叠距离可以通过定时背面曝光，显影剂的应用，烘烤或蚀刻剂的应用来控制。

    Highly stable and efficient OLEDs with a phosphorescent-doped mixed layer architecture
    9.
    发明授权
    Highly stable and efficient OLEDs with a phosphorescent-doped mixed layer architecture 有权
    具有磷光掺杂混合层结构的高度稳定和高效的OLED

    公开(公告)号：US06803720B2

    公开(公告)日：2004-10-12

    申请号：US09738429

    申请日：2000-12-15

    申请人： Raymond C. Kwong ,  Michael G. Hack ,  Theodore Zhou ,  Julia J. Brown ,  Tan D. Ngo

    发明人： Raymond C. Kwong ,  Michael G. Hack ,  Theodore Zhou ,  Julia J. Brown ,  Tan D. Ngo

    IPC分类号： H05B3300

    CPC分类号： H01L51/5016 ,  H01L51/0059 ,  H01L51/0078 ,  H01L51/0081 ,  H01L51/5024 ,  H01L2251/5384

    摘要： A highly stable and efficient organic light emitting device with a phosphorescent-doped mixed layer architecture comprises an anode layer; hole injecting layer over the anode layer; a mixed layer over the hole injecting layer, the mixed layer comprising an organic small molecule hole transporting material, an organic small molecule electron transporting material and a phosphorescent dopant; and a cathode layer over the mixed layer. An electron transporting layer may be present between the mixed layer and the cathode layer and a hole transporting layer may be present between the hole injecting layer and the mixed layer.

    摘要翻译： 具有磷光掺杂混合层结构的高度稳定和高效的有机发光器件包括阳极层; 阳极层上的空穴注入层; 空穴注入层上的混合层，所述混合层包含有机小分子空穴传输材料，有机小分子电子传输材料和磷光掺杂剂; 和混合层上的阴极层。 电子传输层可以存在于混合层和阴极层之间，空穴传输层可以存在于空穴注入层和混合层之间。