公开(公告)号：US20090244864A1

公开(公告)日：2009-10-01

申请号：US12320794

申请日：2009-02-04

申请人： Woon-Chun Kim ,  Sung Yi ,  Hwa-Sun Park ,  Sang-Chul Lee ,  Jong-Woo Han ,  Young-Do Kweon

发明人： Woon-Chun Kim ,  Sung Yi ,  Hwa-Sun Park ,  Sang-Chul Lee ,  Jong-Woo Han ,  Young-Do Kweon

IPC分类号： H05K1/18 ,  B32B7/00 ,  B32B37/02

CPC分类号： H05K1/162 ,  H05K3/108 ,  H05K3/386 ,  H05K3/387 ,  H05K3/4602 ,  H05K3/4626 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09672 ,  Y10T428/24355

摘要： Disclosed are a substrate for a capacitor-embedded printed circuit board, a capacitor-embedded printed circuit board, and a manufacturing method thereof. The capacitor-embedded printed circuit board can include a core board, an insulation resin layer, which is stacked on the core board, a first electrode and a first circuit pattern, which are buried in the insulation resin layer, a dielectric layer, which is stacked on a surface of the insulation resin layer, a first adhesive resin layer, which is stacked on the dielectric layer, and a second electrode and a second circuit pattern, which are formed on a surface of the first adhesive resin layer to correspond with the first electrode. With the present invention, the manufacturing process can be simplified and the reliability of products can be improved by reducing the variation of the capacitor (C).

摘要翻译： 公开了用于电容器嵌入式印刷电路板的基板，电容器嵌入式印刷电路板及其制造方法。 电容器嵌入式印刷电路板可以包括堆叠在芯板上的芯板，绝缘树脂层，埋在绝缘树脂层中的第一电极和第一电路图案，介电层，其是 堆叠在绝缘树脂层的表面上，堆叠在电介质层上的第一粘合树脂层和形成在第一粘合树脂层的表面上的第二电极和第二电路图案，以对应于 第一电极。 利用本发明，可以简化制造工艺，并且可以通过减小电容器（C）的变化来提高产品的可靠性。

公开(公告)号：US20120152886A1

公开(公告)日：2012-06-21

申请号：US13403211

申请日：2012-02-23

申请人： Woon-Chun KIM ,  Sung Yi ,  Hwa-Sun Park ,  Sang-Chul Lee ,  Jong-Woo Han ,  Young-Do Kweon

发明人： Woon-Chun KIM ,  Sung Yi ,  Hwa-Sun Park ,  Sang-Chul Lee ,  Jong-Woo Han ,  Young-Do Kweon

IPC分类号： H01G13/00

CPC分类号： H05K1/162 ,  H05K3/108 ,  H05K3/386 ,  H05K3/387 ,  H05K3/4602 ,  H05K3/4626 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09672 ,  Y10T428/24355

摘要： A method of manufacturing a capacitor-embedded printed circuit board, the method including providing a substrate on which a first metal layer, a dielectric layer and an adhesive resin layer are stacked on the order thereof; etching a part of the first metal layer to form a first electrode and a first circuit pattern; compressing a surface of the substrate, on which the first electrode is formed, onto a core board by interposing an insulation resin layer; forming a second electrode and a second circuit pattern on the adhesive resin layer; stacking an insulation board on the substrate such that the second electrode and the second circuit pattern are covered; and forming a third circuit pattern on the insulation board.

摘要翻译： 一种制造电容器嵌入式印刷电路板的方法，该方法包括提供其上第一金属层，电介质层和粘合树脂层按顺序堆叠的基板; 蚀刻第一金属层的一部分以形成第一电极和第一电路图案; 通过插入绝缘树脂层将形成有第一电极的基板的表面压在芯板上; 在所述粘合树脂层上形成第二电极和第二电路图案; 在所述基板上堆叠绝缘板，使得所述第二电极和所述第二电路图案被覆盖; 以及在所述绝缘板上形成第三电路图案。

公开(公告)号：US20110099779A1

公开(公告)日：2011-05-05

申请号：US12929234

申请日：2011-01-10

申请人： Woon-Chun Kim ,  Sung Yi ,  Hwa-Sun Park ,  Hong-Won Kim ,  Dae-Jun Kim ,  Jin-Seon Park

发明人： Woon-Chun Kim ,  Sung Yi ,  Hwa-Sun Park ,  Hong-Won Kim ,  Dae-Jun Kim ,  Jin-Seon Park

IPC分类号： H01G7/00

CPC分类号： H05K1/162 ,  H05K3/108 ,  H05K3/386 ,  H05K3/4626 ,  H05K2201/0195 ,  H05K2201/09672 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49167

摘要： A method of manufacturing a capacitor-embedded printed circuit board that includes fabricating a capacitor substrate having at least one inner electrode formed on one side of a dielectric layer; aligning a semi-cured insulation layer with one side of a core layer, and aligning the capacitor substrate with the semi-cured insulation layer such that the inner electrode faces the semi-cured insulation layer; and collectively stacking the core layer, the semi-cured insulation layer, and the capacitor substrate.

摘要翻译： 一种制造电容器嵌入式印刷电路板的方法，其包括制造具有形成在电介质层的一侧上的至少一个内部电极的电容器基板; 将半固化绝缘层与芯层的一侧对准，并将电容器基板与半固化绝缘层对准，使得内电极面向半固化绝缘层; 并且集中地堆叠芯层，半固化绝缘层和电容器基板。

公开(公告)号：US07886414B2

公开(公告)日：2011-02-15

申请号：US12081862

申请日：2008-04-22

申请人： Woon-Chun Kim ,  Sung Yi ,  Hwa-Sun Park ,  Hong-Won Kim ,  Dae-Jun Kim ,  Jin-Seon Park

发明人： Woon-Chun Kim ,  Sung Yi ,  Hwa-Sun Park ,  Hong-Won Kim ,  Dae-Jun Kim ,  Jin-Seon Park

IPC分类号： H01G7/00

CPC分类号： H05K1/162 ,  H05K3/108 ,  H05K3/386 ,  H05K3/4626 ,  H05K2201/0195 ,  H05K2201/09672 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49167

摘要： A method of manufacturing a capacitor-embedded PCB is disclosed. The method may include fabricating a capacitor substrate having at least one inner electrode formed on one side of a dielectric layer; aligning a semi-cured insulation layer with one side of a core layer, and aligning the capacitor substrate with the semi-cured insulation layer such that the inner electrode faces the semi-cured insulation layer; and collectively stacking the core layer, the semi-cured insulation layer, and the capacitor substrate.

摘要翻译： 公开了一种制造电容器嵌入式PCB的方法。 该方法可以包括制造具有形成在电介质层的一侧上的至少一个内部电极的电容器基板; 将半固化绝缘层与芯层的一侧对准，并将电容器基板与半固化绝缘层对准，使得内电极面向半固化绝缘层; 并且集中地堆叠芯层，半固化绝缘层和电容器基板。

公开(公告)号：US08302270B2

公开(公告)日：2012-11-06

申请号：US12929234

申请日：2011-01-10

申请人： Woon-Chun Kim ,  Sung Yi ,  Hwa-Sun Park ,  Hong-Won Kim ,  Dae-Jun Kim ,  Jin-Seon Park

发明人： Woon-Chun Kim ,  Sung Yi ,  Hwa-Sun Park ,  Hong-Won Kim ,  Dae-Jun Kim ,  Jin-Seon Park

IPC分类号： H01G7/00

CPC分类号： H05K1/162 ,  H05K3/108 ,  H05K3/386 ,  H05K3/4626 ,  H05K2201/0195 ,  H05K2201/09672 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49167

摘要： A method of manufacturing a capacitor-embedded printed circuit board that includes fabricating a capacitor substrate having at least one inner electrode formed on one side of a dielectric layer; aligning a semi-cured insulation layer with one side of a core layer, and aligning the capacitor substrate with the semi-cured insulation layer such that the inner electrode faces the semi-cured insulation layer; and collectively stacking the core layer, the semi-cured insulation layer, and the capacitor substrate.

摘要翻译： 一种制造电容器嵌入式印刷电路板的方法，其包括制造具有形成在电介质层的一侧上的至少一个内部电极的电容器基板; 将半固化绝缘层与芯层的一侧对准，并将电容器基板与半固化绝缘层对准，使得内电极面向半固化绝缘层; 并且集中地堆叠芯层，半固化绝缘层和电容器基板。

公开(公告)号：US20090025195A1

公开(公告)日：2009-01-29

申请号：US12081862

申请日：2008-04-22

申请人： Woon-Chun Kim ,  Sung Yi ,  Hwa-Sun Park ,  Hong-Won Kim ,  Dae-Jun Kim ,  Jin-Seon Park

发明人： Woon-Chun Kim ,  Sung Yi ,  Hwa-Sun Park ,  Hong-Won Kim ,  Dae-Jun Kim ,  Jin-Seon Park

IPC分类号： H01G9/00

CPC分类号： H05K1/162 ,  H05K3/108 ,  H05K3/386 ,  H05K3/4626 ,  H05K2201/0195 ,  H05K2201/09672 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49167

摘要： A method of manufacturing a capacitor-embedded PCB is disclosed. The method may include fabricating a capacitor substrate having at least one inner electrode formed on one side of a dielectric layer; aligning a semi-cured insulation layer with one side of a core layer, and aligning the capacitor substrate with the semi-cured insulation layer such that the inner electrode faces the semi-cured insulation layer; and collectively stacking the core layer, the semi-cured insulation layer, and the capacitor substrate.

摘要翻译： 公开了一种制造电容器嵌入式PCB的方法。 该方法可以包括制造具有形成在电介质层的一侧上的至少一个内部电极的电容器基板; 将半固化绝缘层与芯层的一侧对准，并将电容器基板与半固化绝缘层对准，使得内电极面向半固化绝缘层; 并且集中地堆叠芯层，半固化绝缘层和电容器基板。

公开(公告)号：US07730612B2

公开(公告)日：2010-06-08

申请号：US12081858

申请日：2008-04-22

申请人： Hwa-Sun Park ,  Sung Yi ,  Sang-Chul Lee ,  Jong-Woon Kim ,  Yul-Kyo Chung

发明人： Hwa-Sun Park ,  Sung Yi ,  Sang-Chul Lee ,  Jong-Woon Kim ,  Yul-Kyo Chung

IPC分类号： H05K3/30

CPC分类号： H05K1/185 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24227 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H05K1/056 ,  H05K3/445 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0969 ,  H05K2203/1469 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49139

摘要： A method of manufacturing a component-embedded printed circuit board is disclosed. The method includes: forming a blind hole in the first metal layer such that the first insulation layer is exposed, for a metal-clad laminate that includes a first metal layer stacked over a first insulation layer, securing a component to the first insulation layer by embedding the component in the blind hole, stacking a second insulation layer and a second metal layer on either side of the metal-clad laminate, and forming circuit patterns by removing portions of the metal layers.

摘要翻译： 公开了一种制造嵌入元件的印刷电路板的方法。 该方法包括：在第一绝缘层上形成盲孔以使第一绝缘层被暴露，对于包覆层叠在第一绝缘层上的第一金属层的覆金属层压板，将部件固定在第一绝缘层上 将所述部件嵌入所述盲孔中，在所述覆金属层压板的任一侧堆叠第二绝缘层和第二金属层，以及通过去除所述金属层的一部分来形成电路图案。

公开(公告)号：US20090049686A1

公开(公告)日：2009-02-26

申请号：US12081858

申请日：2008-04-22

申请人： Hwa-Sun Park ,  Sung Yi ,  Sang-Chul Lee ,  Jong-Woon Kim ,  Yul-Kyo Chung

发明人： Hwa-Sun Park ,  Sung Yi ,  Sang-Chul Lee ,  Jong-Woon Kim ,  Yul-Kyo Chung

IPC分类号： H05K3/30

CPC分类号： H05K1/185 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24227 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H05K1/056 ,  H05K3/445 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0969 ,  H05K2203/1469 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49139

摘要： A method of manufacturing a component-embedded printed circuit board is disclosed. The method includes: forming a blind hole in the first metal layer such that the first insulation layer is exposed, for a metal-clad laminate that includes a first insulation layer stacked over a first metal layer, securing a component to the first insulation layer by embedding the component in the blind hole, stacking a second insulation layer and a second metal layer on either side of the metal-clad laminate, and forming circuit patterns by removing portions of the metal layers.

摘要翻译： 公开了一种制造嵌入元件的印刷电路板的方法。 该方法包括：在第一金属层上形成盲孔以使第一绝缘层暴露，对于包覆层叠在第一金属层上的第一绝缘层的覆金属层压板，将部件固定到第一绝缘层上 将所述部件嵌入所述盲孔中，在所述覆金属层压板的任一侧堆叠第二绝缘层和第二金属层，以及通过去除所述金属层的一部分来形成电路图案。

公开(公告)号：US07663250B2

公开(公告)日：2010-02-16

申请号：US12230793

申请日：2008-09-04

申请人： Hyung Jin Jeon ,  Sung Yi ,  Jong Yun Lee ,  Young Do Kweon ,  Jong Hwan Baek

发明人： Hyung Jin Jeon ,  Sung Yi ,  Jong Yun Lee ,  Young Do Kweon ,  Jong Hwan Baek

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/12 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： A wafer level package and a manufacturing method thereof capable of reducing stress between an under bump metal and a bump. The wafer level package includes a substrate provided with a plurality of chip pads on a top surface; a first passivation layer to expose the chip pads; vias connected to the chip pads by passing through the first passivation layer; a metal wiring layer formed on the first passivation layer and connected to the vias; an under bump metal formed on the first passivation layer to be connected to the metal wiring layer and having a buffer pattern separated through a trench on a center; a second passivation layer formed on the first passivation layer to expose the under bump metal; a first bump formed on the buffer pattern; and a second bump filling the trench and formed on the first bump and the under bump metal.

摘要翻译： 一种晶片级封装及其制造方法，能够减少凸块之间的应力。 晶片级封装包括在顶表面上设置有多个芯片焊盘的衬底; 第一钝化层以暴露所述芯片焊盘; 通过穿过第一钝化层连接到芯片焊盘的通孔; 形成在所述第一钝化层上并连接到所述通孔的金属布线层; 形成在所述第一钝化层上以连接到所述金属布线层并且具有通过中心的沟槽分离的缓冲图案的下凸块金属; 形成在所述第一钝化层上以暴露所述下凸块金属的第二钝化层; 形成在缓冲图案上的第一凸起; 以及填充所述沟槽并形成在所述第一凸块和所述下凸块金属上的第二凸块。

公开(公告)号：US07632709B2

公开(公告)日：2009-12-15

申请号：US12149106

申请日：2008-04-25

申请人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

发明人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

IPC分类号： H01L21/00

CPC分类号： H01L23/3114 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/24 ,  H01L24/27 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2224/24227 ,  H01L2224/274 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517

摘要： A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased.