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    Fast MTJ Switching Write Circuit For MRAM Array
    2.
    发明申请
    Fast MTJ Switching Write Circuit For MRAM Array 审中-公开
    用于MRAM阵列的快速MTJ切换写入电路

    公开(公告)号：US20130028010A1

    公开(公告)日：2013-01-31

    申请号：US13193689

    申请日：2011-07-29

    申请人： Xia Li ,  Xiaochun Zhu ,  Wuyang Hao

    发明人： Xia Li ,  Xiaochun Zhu ,  Wuyang Hao

    IPC分类号： G11C11/16

    CPC分类号： G11C11/1657 ,  G11C11/1659 ,  G11C11/1675

    摘要： A transmission gate is arranged between a current source and a resistive memory element, a PMOS gate of the transmission gate has no source loading effect and a write current passes from the current source, and in a first direction through the resistive memory element, setting the resistive memory element to a magnetization state. An NMOS gate of the of the transmission gate has no source loading effect and another write current, passes through the resistive memory element, in a second direction opposite the first direction, and through the transmission gate, setting the resistive memory element to an opposite magnetization state.

    摘要翻译： 传输门被布置在电流源和电阻存储元件之间，传输门的PMOS栅极没有源负载效应，并且写入电流从电流源流过，并且在第一方向通过电阻存储元件，将 电阻性存储元件达到磁化状态。 传输门的NMOS栅极没有源负载效应，而另一写入电流在与第一方向相反的第二方向上通过电阻性存储元件，并且通过传输门将电阻性存储元件设置为相反的磁化 州。

    Magnetic element with storage layer materials
    4.
    发明授权
    Magnetic element with storage layer materials 有权
    磁性元件与存储层材料

    公开(公告)号：US08536669B2

    公开(公告)日：2013-09-17

    申请号：US12352648

    申请日：2009-01-13

    申请人： Xiaochun Zhu ,  Xia Li ,  Seung H. Kang

    发明人： Xiaochun Zhu ,  Xia Li ,  Seung H. Kang

    IPC分类号： H01L29/82 ,  G11B5/33 ,  G11C11/02

    CPC分类号： H01L43/10 ,  G11C11/161 ,  H01L43/12

    摘要： According to an embodiment of the invention, a magnetic tunnel junction (MTJ) element includes a reference ferromagnetic layer, a storage ferromagnetic layer, and an insulating layer. The storage ferromagnetic layer includes a CoFeB sub-layer coupled to a CoFe sub-layer and/or a NiFe sub-layer through a non-magnetic sub-layer. The insulating layer is disposed between the reference and storage ferromagnetic layers.

    摘要翻译： 根据本发明的实施例，磁性隧道结（MTJ）元件包括参考铁磁层，存储铁磁层和绝缘层。 存储铁磁层包括通过非磁性子层耦合到CoFe子层和/或NiFe子层的CoFeB子层。 绝缘层设置在参考和存储铁磁层之间。

    Magnetic random access memory
    5.
    发明授权
    Magnetic random access memory 有权
    磁性随机存取存储器

    公开(公告)号：US08421137B2

    公开(公告)日：2013-04-16

    申请号：US12769353

    申请日：2010-04-28

    申请人： Xia Li ,  Seung H. Kang ,  Xiaochun Zhu

    发明人： Xia Li ,  Seung H. Kang ,  Xiaochun Zhu

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L43/12 ,  G11C11/16 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/312 ,  H01L21/31612 ,  H01L21/6715 ,  H01L27/222

    摘要： A device includes a magnetic tunnel junction (MTJ) structure and a cap layer in contact with the MTJ structure. The device also includes a spin-on material layer in contact with a sidewall portion of the cap layer and a conducting layer in contact with at least the spin-on material layer and a portion of the MTJ structure. The cap layer has been etched to expose a portion of an electrode contact layer of the MTJ structure. The conducting layer is in electrical contact with the exposed portion of the electrode contact layer of the MTJ structure.

    摘要翻译： 一种装置包括磁隧道结（MTJ）结构和与MTJ结构接触的盖层。 该装置还包括与盖层的侧壁部分接触的旋涂材料层和与至少旋涂材料层和MTJ结构的一部分接触的导电层。 已经蚀刻了盖层以暴露MTJ结构的电极接触层的一部分。 导电层与MTJ结构的电极接触层的暴露部分电接触。

    Configurable Memory Array
    6.
    发明申请
    Configurable Memory Array 有权
    可配置内存阵列

    公开(公告)号：US20120218805A1

    公开(公告)日：2012-08-30

    申请号：US13034763

    申请日：2011-02-25

    申请人： Jung Pill Kim ,  Hari M. Rao ,  Xiaochun Zhu ,  Xia Li ,  Seung H. Kang

    发明人： Jung Pill Kim ,  Hari M. Rao ,  Xiaochun Zhu ,  Xia Li ,  Seung H. Kang

    IPC分类号： G11C5/06 ,  H05K13/00 ,  G11C29/08 ,  G11C11/00 ,  G11C7/00

    CPC分类号： G11C11/1677 ,  G11C8/08 ,  G11C8/14 ,  G11C11/16 ,  G11C11/161 ,  G11C29/18 ,  G11C29/30 ,  G11C2029/1202 ,  G11C2029/2602 ,  H01L43/12

    摘要： Embodiments disclosed include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a second subset of storage elements coupled to the memory array. The memory array further includes a plurality of bit cells, each including one storage element from the second subset of storage elements coupled to at least two transistors. The bit cells are coupled to the plurality of bit lines and the plurality source lines. Each transistor is coupled to one word line. The memory array can further include logic to select a high performance mode and a high density mode.

    摘要翻译： 所公开的实施例包括具有多个位线和多个排列成列的源极线的存储器阵列。 多行字线被排列成行。 多个存储元件具有与存储器阵列电分离的存储元件的第一子集和耦合到存储器阵列的存储元件的第二子集。 存储器阵列还包括多个位单元，每个位单元包括来自耦合到至少两个晶体管的存储元件的第二子集的一个存储元件。 位单元耦合到多个位线和多个源极线。 每个晶体管耦合到一个字线。 存储器阵列还可以包括选择高性能模式和高密度模式的逻辑。

    Magnetic Element With Storage Layer Materials
    9.
    发明申请
    Magnetic Element With Storage Layer Materials 有权
    磁性元素与存储层材料

    公开(公告)号：US20100176471A1

    公开(公告)日：2010-07-15

    申请号：US12352648

    申请日：2009-01-13

    申请人： Xiaochun Zhu ,  Xia Li ,  Seung H. Kang

    发明人： Xiaochun Zhu ,  Xia Li ,  Seung H. Kang

    IPC分类号： H01L29/82 ,  H01L21/00

    CPC分类号： H01L43/10 ,  G11C11/161 ,  H01L43/12

    摘要： According to an embodiment of the invention, a magnetic tunnel junction (MTJ) element includes a reference ferromagnetic layer, a storage ferromagnetic layer, and an insulating layer. The storage ferromagnetic layer includes a CoFeB sub-layer coupled to a CoFe sub-layer and/or a NiFe sub-layer through a non-magnetic sub-layer. The insulating layer is disposed between the reference and storage ferromagnetic layers.

    摘要翻译： 根据本发明的实施例，磁性隧道结（MTJ）元件包括参考铁磁层，存储铁磁层和绝缘层。 存储铁磁层包括通过非磁性子层耦合到CoFe子层和/或NiFe子层的CoFeB子层。 绝缘层设置在参考和存储铁磁层之间。

    Non-volatile memory array configurable for high performance and high density
    10.
    发明授权
    Non-volatile memory array configurable for high performance and high density 有权
    非易失性存储器阵列可配置为高性能和高密度

    公开(公告)号：US08587982B2

    公开(公告)日：2013-11-19

    申请号：US13034763

    申请日：2011-02-25

    申请人： Jung Pill Kim ,  Hari M. Rao ,  Xiaochun Zhu ,  Xia Li ,  Seung H. Kang

    发明人： Jung Pill Kim ,  Hari M. Rao ,  Xiaochun Zhu ,  Xia Li ,  Seung H. Kang

    IPC分类号： G11C5/06

    CPC分类号： G11C11/1677 ,  G11C8/08 ,  G11C8/14 ,  G11C11/16 ,  G11C11/161 ,  G11C29/18 ,  G11C29/30 ,  G11C2029/1202 ,  G11C2029/2602 ,  H01L43/12

    摘要： Embodiments include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a second subset of storage elements coupled to the memory array. The memory array further includes a plurality of bit cells, each including one storage element from the second subset of storage elements coupled to at least two transistors. The bit cells are coupled to the plurality of bit lines and the plurality source lines. Each transistor is coupled to one word line. The memory array can further include logic to select a high performance mode and a high density mode.

    摘要翻译： 实施例包括具有多个位线和多个排列成列的源极线的存储器阵列。 多行字线被排列成行。 多个存储元件具有与存储器阵列电分离的存储元件的第一子集和耦合到存储器阵列的存储元件的第二子集。 存储器阵列还包括多个位单元，每个位单元包括来自耦合到至少两个晶体管的存储元件的第二子集的一个存储元件。 位单元耦合到多个位线和多个源极线。 每个晶体管耦合到一个字线。 存储器阵列还可以包括选择高性能模式和高密度模式的逻辑。