CMOS DEVICES INCORPORATING HYBRID ORIENTATION TECHNOLOGY (HOT) WITH EMBEDDED CONNECTORS
    8.
    发明申请
    CMOS DEVICES INCORPORATING HYBRID ORIENTATION TECHNOLOGY (HOT) WITH EMBEDDED CONNECTORS 有权
    嵌入式连接器的混合定向技术(HOT)的CMOS器件

    公开(公告)号:US20090321794A1

    公开(公告)日:2009-12-31

    申请号:US12555350

    申请日:2009-09-08

    IPC分类号: H01L29/04

    摘要: The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.

    摘要翻译: 本发明涉及具有混合通道取向并由嵌入在半导体衬底中的导电连接器连接的诸如n-FET和p-FET的互补器件。 具体地,半导体衬底具有至少具有不同表面晶取向(即混合取向)的第一和第二器件区域。 n-FET形成在第一和第二器件区域中的一个处,并且p-FET形成在第一和第二器件区域中的另一个处。 n-FET和p-FET通过位于第一和第二器件区域之间的导电连接器电连接并嵌入在半导体衬底中。 优选地,介电隔离件首先设置在第一和第二器件区域之间并且凹入以在它们之间形成间隙。 然后将导电连接器形成在凹入的电介质间隔物上方的间隙中。

    SEMICONDUCTOR STRUCTURES INCLUDING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND METHODS FOR FABRICATION THEREOF
    10.
    发明申请
    SEMICONDUCTOR STRUCTURES INCLUDING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND METHODS FOR FABRICATION THEREOF 失效
    包括多个晶体学方位的半导体结构及其制造方法

    公开(公告)号:US20080083952A1

    公开(公告)日:2008-04-10

    申请号:US11538963

    申请日:2006-10-05

    IPC分类号: H01L27/12 H01L21/84

    摘要: Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from a surface semiconductor layer having a second crystallographic orientation within the semiconductor-on-insulator structure. A recess of the semiconductor surface layer with respect to a buried dielectric layer thereunder and a hard mask layer thereover provides for inhibited second crystallographic phase growth within the epitaxial surface semiconductor layer.

    摘要翻译: 半导体结构及其制造方法基于外延表面半导体层在具有第一晶体取向的半导体衬底上外延生长。 半导体衬底暴露在绝缘体内半导体结构内的孔内。 外延表面半导体层与绝缘体半导体结构内的具有第二结晶取向的表面半导体层交替接触或隔离。 半导体表面层相对于其下方的掩埋介电层的凹部和其上的硬掩模层提供了外延表面半导体层内的抑制的第二结晶相生长。