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1.发明申请公开(公告)号：US20100044870A1
公开(公告)日：2010-02-25
申请号：US12309207
申请日：2007-07-06
CPC分类号： H01L24/90 , H01L21/563 , H01L24/11 , H01L24/16 , H01L24/28 , H01L24/83 , H01L25/0657 , H01L2224/0401 , H01L2224/0603 , H01L2224/13011 , H01L2224/13012 , H01L2224/13015 , H01L2224/13017 , H01L2224/13018 , H01L2224/13099 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/16 , H01L2224/24145 , H01L2224/73203 , H01L2224/83192 , H01L2224/83194 , H01L2224/838 , H01L2224/9202 , H01L2225/06551 , H01L2225/06575 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/00012
摘要： An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.
摘要翻译： 提供半导体芯片的电极连接结构，以在不使用凸块的情况下实现具有低应力的高度可靠的电连接。 导电构件可用于这种电极连接结构。 提供了半导体器件，其中半导体芯片被布置成层，而不向半导体芯片提供通孔，并且提供了制造这种半导体器件的方法。 形成在布置在下层的第一电极和上层的第二电极之间的粘合剂层中的水平凹部的一部分或全部表面设置有用于将第一电极和第二电极连接的导电构件 第二电极。
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公开(公告)号：US08367468B2
公开(公告)日：2013-02-05
申请号：US13096496
申请日：2011-04-28
CPC分类号： H01L24/90 , H01L21/563 , H01L24/11 , H01L24/16 , H01L24/28 , H01L24/83 , H01L25/0657 , H01L2224/0401 , H01L2224/0603 , H01L2224/13011 , H01L2224/13012 , H01L2224/13015 , H01L2224/13017 , H01L2224/13018 , H01L2224/13099 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/16 , H01L2224/24145 , H01L2224/73203 , H01L2224/83192 , H01L2224/83194 , H01L2224/838 , H01L2224/9202 , H01L2225/06551 , H01L2225/06575 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/00012
摘要： An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.
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3.发明授权Electroless gold plating solution for forming fine gold structure, method of forming fine gold structure using same, and fine gold structure formed using same 有权用于形成细金结构的无电镀金液，使用其形成精金结构的方法，以及使用其形成的精金结构公开(公告)号：US09345145B2
公开(公告)日：2016-05-17
申请号：US13255392
申请日：2010-03-10
申请人： Ryota Iwai , Tomoaki Tokuhisa , Masaru Kato , Tokihiko Yokoshima , Masahiro Aoyagi , Yasuhiro Yamaji , Katsuya Kikuchi , Hiroshi Nakagawa
发明人： Ryota Iwai , Tomoaki Tokuhisa , Masaru Kato , Tokihiko Yokoshima , Masahiro Aoyagi , Yasuhiro Yamaji , Katsuya Kikuchi , Hiroshi Nakagawa
CPC分类号： H05K3/187 , C23C18/1605 , C23C18/1607 , C23C18/165 , C23C18/1834 , C23C18/1844 , C23C18/1851 , C23C18/44
摘要： An electroless gold plating solution with which one or more openings formed in a resist overlying a substrate can be filled in a short time, the openings having a width on the order of micrometer, in particular, 100 μm or smaller, in terms of the width of the exposed substrate area, and having a height of 3 μm or larger. The electroless gold plating solution contains a deposition accelerator for deposition in fine areas, and a microfine pattern of 100 μm or finer is formed therefrom.
摘要翻译： 可以在短时间内填充形成在覆盖基板的抗蚀剂中形成的一个或多个开口的无电镀金液，所述开口宽度在数量级以上，特别是100μm以下 的暴露的基板区域，并且具有3μm或更大的高度。 无电镀金液含有用于在微细区域中沉积的沉积促进剂，由此形成100μm以上的微细图案。
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4.发明授权公开(公告)号：US08399979B2
公开(公告)日：2013-03-19
申请号：US12309207
申请日：2007-07-06
CPC分类号： H01L24/90 , H01L21/563 , H01L24/11 , H01L24/16 , H01L24/28 , H01L24/83 , H01L25/0657 , H01L2224/0401 , H01L2224/0603 , H01L2224/13011 , H01L2224/13012 , H01L2224/13015 , H01L2224/13017 , H01L2224/13018 , H01L2224/13099 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/16 , H01L2224/24145 , H01L2224/73203 , H01L2224/83192 , H01L2224/83194 , H01L2224/838 , H01L2224/9202 , H01L2225/06551 , H01L2225/06575 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/00012
摘要： An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.
摘要翻译： 提供半导体芯片的电极连接结构，以在不使用凸块的情况下实现具有低应力的高度可靠的电连接。 导电构件可用于这种电极连接结构。 提供了半导体器件，其中半导体芯片被布置成层，而不向半导体芯片提供通孔，并且提供了制造这种半导体器件的方法。 形成在布置在下层的第一电极和上层的第二电极之间的粘合剂层中的水平凹部的一部分或全部表面设置有用于将第一电极和第二电极连接的导电构件 第二电极。
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5.发明申请公开(公告)号：US20120108008A1
公开(公告)日：2012-05-03
申请号：US13096496
申请日：2011-04-28
IPC分类号： H01L21/50
CPC分类号： H01L24/90 , H01L21/563 , H01L24/11 , H01L24/16 , H01L24/28 , H01L24/83 , H01L25/0657 , H01L2224/0401 , H01L2224/0603 , H01L2224/13011 , H01L2224/13012 , H01L2224/13015 , H01L2224/13017 , H01L2224/13018 , H01L2224/13099 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/16 , H01L2224/24145 , H01L2224/73203 , H01L2224/83192 , H01L2224/83194 , H01L2224/838 , H01L2224/9202 , H01L2225/06551 , H01L2225/06575 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/00012
摘要： An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.
摘要翻译： 提供半导体芯片的电极连接结构，以在不使用凸块的情况下实现具有低应力的高度可靠的电连接。 导电构件可用于这种电极连接结构。 提供了半导体器件，其中半导体芯片被布置成层，而不向半导体芯片提供通孔，并且提供了制造这种半导体器件的方法。 形成在布置在下层的第一电极和上层的第二电极之间的粘合剂层中的水平凹部的一部分或全部表面设置有导电构件，用于将第一电极和 第二电极。
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公开(公告)号：US20050110149A1
公开(公告)日：2005-05-26
申请号：US10965868
申请日：2004-10-18
IPC分类号： C23C18/16 , C23C18/20 , C23C18/40 , C25D7/12 , H01L21/316 , H01L21/3205 , H01L21/4763 , H01L21/768 , H01L23/52 , H05K3/38 , H05K3/46
CPC分类号： H01L21/76843 , H01L21/76801 , H01L21/76808 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L21/76855 , H01L21/76864 , H01L21/76874 , H05K3/389 , H05K3/465 , Y10T29/49155
摘要： A silica-based interlayer insulating layer having a low dielectric constant is formed with SOG material on a substrate, in which a wiring-layer forming space is then formed. If necessary, a UV ray irradiation is performed under an oxidizing atmosphere. A Si—OH bond is formed on a surface of the insulating layer. A monomolecular layer film is then adhered to the inner surface of the space, which is then modified to be a catalyst with a solution containing Pd compound. On the catalyst monomolecular layer, a copper-diffusion-resistant film is formed by electroless plating, on which a copper plate is then formed as a wiring layer.
摘要翻译： 在基板上用SOG材料形成具有低介电常数的二氧化硅基层间绝缘层，然后形成布线层形成空间。 如果需要，在氧化气氛下进行紫外线照射。 在绝缘层的表面上形成Si-OH键。 然后将单分子层膜粘合到空间的内表面，然后将其用含有Pd化合物的溶液改性为催化剂。 在催化剂单分子层上，通过化学镀形成铜扩散膜，然后在其上形成铜板作为布线层。
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公开(公告)号：US20180156872A1
公开(公告)日：2018-06-07
申请号：US15819663
申请日：2017-11-21
申请人： Yasumasa Oguma , Tetsuya Osaka , Shingo Tsuda , Kazuaki Utsumi , Tokihiko Yokoshima , Daikichi Mukoyama
发明人： Yasumasa Oguma , Tetsuya Osaka , Shingo Tsuda , Kazuaki Utsumi , Tokihiko Yokoshima , Daikichi Mukoyama
IPC分类号： G01R31/36
CPC分类号： G01R31/389 , G01R31/3648 , G01R31/392
摘要： A battery state estimating apparatus is provided with: an acquirer configured to obtain a plurality of complex impedances of a battery at a plurality of different temperatures; a calculator configured to calculate a slope of a straight line connecting values of the obtained plurality of complex impedances at a first predetermined frequency on a complex plane having an axis that is a real component of the complex impedance and an axis that is an imaginary component of the complex impedance, as a slope of the complex impedance; a storage configured to store in advance a relation between the slope of the complex impedance and a battery state associated with the battery; and an estimator configured to estimate the battery state on the basis of the calculated slope of the complex impedance and the stored relation.
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8.发明申请公开(公告)号：US20050249984A1
公开(公告)日：2005-11-10
申请号：US11118468
申请日：2005-05-02
申请人： Masahiro Ohmori , Hiroshi Ohta , Tetsuya Osaka , Toru Asahi , Tokihiko Yokoshima
发明人： Masahiro Ohmori , Hiroshi Ohta , Tetsuya Osaka , Toru Asahi , Tokihiko Yokoshima
CPC分类号： G11B5/8404 , G11B5/667 , G11B5/7325 , G11B5/7379 , G11B5/858
摘要： A perpendicular magnetic recording medium includes a non-magnetic substrate, and at least a soft magnetic under layer formed of a soft magnetic material, an alignment-regulating layer for regulating the crystal alignment of a layer provided directly thereon, a perpendicular magnetic layer in which easy-magnetization axes are oriented generally perpendicular to the substrate, and a protective layer, the layers and the layer being provided atop the substrate, wherein the soft magnetic under layer exhibits magnetic isotropy or has easy-magnetization axes oriented perpendicular to the substrate. According to the present invention, an undercoat layer having no magnetic domain walls can be formed. When the undercoat layer is employed, there can be provided a perpendicular magnetic recording medium and a perpendicular magnetic recording and reproducing apparatus which exhibit high thermal stability and excellent noise characteristics, and which attain high-density recording.
摘要翻译： 垂直磁记录介质包括非磁性基板，以及至少由软磁材料形成的软磁下层，用于调节直接设置在其上的层的晶体取向的取向调节层，垂直磁性层，其中 容易磁化轴大致垂直于衬底定向，并且保护层，层和层设置在衬底顶部，其中软磁下层表现出磁各向同性或具有垂直于衬底的易磁化轴。 根据本发明，可以形成不具有磁畴壁的底涂层。 当使用底涂层时，可以提供表现出高热稳定性和优异的噪声特性的垂直磁记录介质和垂直磁记录和再现装置，并获得高密度记录。
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公开(公告)号：US07242553B2
公开(公告)日：2007-07-10
申请号：US10935519
申请日：2004-09-07
CPC分类号： G11B5/667 , G11B5/00 , G11B5/7315 , G11B5/74 , G11B5/8404 , G11B2005/001 , G11B2005/0029
摘要： When a soft magnetic layer for a double layer type perpendicular magnetic recording medium is formed by a plating method, there is the problem of the occurrence of an isolated pulse noise called spike noise so that signal reproduction characteristics are lost. In order to solve this problem, provided are a surface-treated substrate for a magnetic recording medium comprising a substrate having a diameter of not more than 90 mm, and a soft magnetic plating layer comprising an alloy of at least two metals selected from the group consisting of Co, Ni and Fe, which is provided above the substrate, wherein the soft magnetic layer has a coercivity of less than 20 oersted (Oe) in a direction that is parallel to a substrate surface, and wherein a ratio of saturation magnetization to residual magnetization in a direction that is parallel to a surface of the substrate is from 4:1 to 4:3; and a magnetic recording medium comprising the magnetic recording medium substrate.
摘要翻译： 当通过电镀法形成双层型垂直磁记录介质的软磁性层时，存在称为尖峰噪声的孤立脉冲噪声的问题，从而丢失了信号再现特性。 为了解决这个问题，提供了一种用于磁记录介质的经表面处理的基板，其包括直径不大于90mm的基板，以及软磁性镀层，该软磁性镀层包含选自以下的至少两种金属 由Co，Ni和Fe构成，其设置在衬底上方，其中软磁性层在平行于衬底表面的方向上具有小于20奥斯特（Oe）的矫顽力，并且其中饱和磁化强度与 在平行于衬底表面的方向上的剩余磁化强度为4:1至4:3; 以及包括磁记录介质基板的磁记录介质。
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公开(公告)号：US07135103B2
公开(公告)日：2006-11-14
申请号：US10816834
申请日：2004-04-05
申请人： Tetsuya Osaka , Tokihiko Yokoshima
发明人： Tetsuya Osaka , Tokihiko Yokoshima
IPC分类号： C25D5/18
CPC分类号： C25D3/562 , C25D5/18 , C25D5/50 , C25D17/002
摘要： A soft magnetic thin film of CoFe alloy having a high Br and low Hc is prepared by furnishing a plating tank including cathode and anode compartments which are separated by a diaphragm or salt bridge so as to permit charge transfer, but inhibit penetration of Fe ions, feeding a plating solution containing Co ions and divalent Fe ions to the cathode compartment, feeding an electrolyte solution to the anode compartment, immersing a substrate in the plating solution, immersing an anode in the electrolyte solution, electroplating, and heat treating the plated film at 100–550° C.; or by immersing a substrate and a soluble anode in a plating solution containing Co ions and divalent Fe ions, electroplating, and heat treating the plated film at 100–550° C.
摘要翻译： 制备具有高Br和低Hc的CoFe合金的软磁性薄膜，其包括通过隔膜或盐桥隔开的阴极和阳极隔室的镀槽，以允许电荷转移，但抑制Fe离子的渗透， 将含有Co离子和二价Fe离子的电镀液供给到阴极室，将电解质溶液供给到阳极室，将基板浸渍在电镀液中，将阳极浸渍在电解液中，电镀，并对镀膜进行热处理 100-550°C。 或者将基板和可溶性阳极浸渍在含有Co离子和二价Fe离子的电镀溶液中，电镀，并在100-550℃下热处理该镀膜。
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