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171 条记录 (耗时 0.02 秒)

    Method of controlling metal thin film formation conditions
    2.
    发明授权
    Method of controlling metal thin film formation conditions 失效
    控制金属薄膜形成条件的方法

    公开(公告)号：US5175115A

    公开(公告)日：1992-12-29

    申请号：US654488

    申请日：1991-02-13

    申请人： Masahiro Abe ,  Yasukazu Mase ,  Toshihiko Katsura ,  Masaharu Aoyama

    发明人： Masahiro Abe ,  Yasukazu Mase ,  Toshihiko Katsura ,  Masaharu Aoyama

    IPC分类号： H01L21/48

    CPC分类号： H01L21/4846

    摘要： Measurement of temperature - internal stress characteristics of an Al thin film formed on an Si substrate is performed. The amount of an impurity or impurities mixed in the thin f ilm can be obtained in accordance with the measured characteristics. A migration start temperature of Al atoms in the thin film in the characteristics obtained when the temperature is increased is fed back as information to the thin film formation step, thereby controlling an impurity amount in an atmosphere for forming the thin film.

    摘要翻译： 进行在Si衬底上形成的Al薄膜的温度 - 内部应力特性的测量。 可以根据测量的特性获得混合在薄膜中的杂质或杂质的量。 当温度升高时获得的特性中，薄膜中Al原子的迁移开始温度作为信息反馈到薄膜形成步骤，从而控制用于形成薄膜的气氛中的杂质量。

    Photolithographic method for manufacturing semiconductor wiring patterns
    3.
    发明授权
    Photolithographic method for manufacturing semiconductor wiring patterns 失效
    用于制造半导体布线图案的光刻方法

    公开(公告)号：US4952528A

    公开(公告)日：1990-08-28

    申请号：US416779

    申请日：1989-10-04

    申请人： Masahiro Abe ,  Yasukazu Mase ,  Toshihiko Katsura

    发明人： Masahiro Abe ,  Yasukazu Mase ,  Toshihiko Katsura

    IPC分类号： H01L21/302 ,  H01L21/027 ,  H01L21/30 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/522

    CPC分类号： H01L21/76802 ,  H01L21/76819 ,  Y10S148/137

    摘要： A method for manufacturing semiconductor devices comprising the steps of forming a first wiring pattern including first and second lower layers on a semiconductor body, forming an insulation film which covers the first wiring pattern, forming a first hole of 1.5 .mu.m and a second hole of 3 .mu.m in first and second areas of the insulation film which lie over the first and second lower layers, forming a second wiring pattern having first and second upper layers respectively connected to the first and second lower layers via the first and second holes. In the method, the hole formation step includes the substeps of forming a resist film which covers the insulation film, forming a resist pattern by effecting the photolithographic process of exposing the insulation film to light by using a mask pattern having a first hole defining area of 1.5 .mu.m and a second hole defining area of 2.4 .mu.m, and etching the insulation film with the resist pattern used as a mask. The exposing light amount used in the resist pattern formation substep is previously determined so that the size of the first hole can be set equal to that of the first hole defining area, and the reduced amount of the second hole defining area is previously determined so that the size of the second hole obtained under the determined exposing light amount can be set to 3 .mu.m.

    Method for planarizing the surface of an interlayer insulating film in a semiconductor device
    7.
    发明授权
    Method for planarizing the surface of an interlayer insulating film in a semiconductor device 失效
    在半导体器件中对层间绝缘膜的表面进行平面化的方法

    公开(公告)号：US4634496A

    公开(公告)日：1987-01-06

    申请号：US797986

    申请日：1985-11-14

    申请人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama

    发明人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama

    IPC分类号： H01L21/3205 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768 ,  B44C1/22 ,  B29C17/08 ,  C03C15/00 ,  C03C25/06

    CPC分类号： H01L21/31116 ,  H01L21/31055 ,  H01L21/76819

    摘要： A method for planarizing the surface of an insulation layer deposited on a first interconnection layer to allow a second interconnection layer deposited thereon without causing a breakage of the second interconnection layer. This method is characterized in that at least two insulation films, different in etching characteristics each other, are first formed on the first interconnection layer, and then a resist layer is deposited on the second insulating film. Subsequently, a portion of the resist layer is etched to expose the top surface of the second insulating film, and the second insulating film is selectively and anisotropically etched using the remaining resist layer as a mask. After removing the first insulating film and the remaining resist mark, a third insulating film is deposited to a thickness sufficient to make flat the surface thereof.

    摘要翻译： 一种用于平坦化沉积在第一互连层上的绝缘层的表面以允许沉积在其上的第二互连层而不引起第二互连层的破损的方法。 该方法的特征在于，首先在第一互连层上形成至少两个彼此不同的蚀刻特性的绝缘膜，然后在第二绝缘膜上沉积抗蚀剂层。 随后，蚀刻抗蚀剂层的一部分以暴露第二绝缘膜的顶表面，并且使用剩余的抗蚀剂层作为掩模来选择性地和各向异性地蚀刻第二绝缘膜。 在去除第一绝缘膜和剩余的抗蚀剂标记之后，沉积第三绝缘膜至足以使其表面平坦的厚度。

    Method of determining end of cleaning of semiconductor manufacturing apparatus
    10.
    发明授权
    Method of determining end of cleaning of semiconductor manufacturing apparatus 失效
    确定半导体制造装置的清洁结束的方法

    公开(公告)号：US5169407A

    公开(公告)日：1992-12-08

    申请号：US623367

    申请日：1990-12-07

    申请人： Yasukazu Mase ,  Masahiro Abe ,  Osamu Hirata

    发明人： Yasukazu Mase ,  Masahiro Abe ,  Osamu Hirata

    IPC分类号： H01L21/00

    CPC分类号： H01L21/67069 ,  H01L21/67011 ,  Y10T29/41

    摘要： In a method for determining an end of cleaning of a semiconductor manufacturing apparatus according to the invention, when the interior of a semiconductor substrate process chamber of the semiconductor manufacturing apparatus is cleaned by dry etching using plasma discharge, a constant current or voltage is supplied from a high-frequency power source to discharge electrodes during plasma discharge, an impedance between the electrodes or a temperature in the process chamber is monitored, a time point at which the impedance or temperature is abruptly changed is detected, and this time point of detection is determined to be an end of cleaning.

    摘要翻译： 在根据本发明的用于确定半导体制造装置的清洁结束的方法中，当通过使用等离子体放电的干蚀刻来清洁半导体制造装置的半导体衬底处理室的内部时，从 在等离子体放电期间放电电极的高频电源，电极之间的阻抗或处理室中的温度被监测，检测到阻抗或温度突然改变的时间点，并且该检测时间点 决心结束清洁。