公开(公告)号：US5153689A

公开(公告)日：1992-10-06

申请号：US404528

申请日：1989-09-08

申请人： Yoshinori Okumura ,  Takayuki Matsukawa ,  Ikuo Ogoh ,  Masao Nagatomo ,  Hideki Genjo ,  Atsushi Hachisuka

发明人： Yoshinori Okumura ,  Takayuki Matsukawa ,  Ikuo Ogoh ,  Masao Nagatomo ,  Hideki Genjo ,  Atsushi Hachisuka

IPC分类号： H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/532 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10808 ,  H01L23/53257 ,  H01L2924/0002

摘要： A memory cell of a semiconductor memory device comprises one MOS transistor (3) and one stacked capacitor (4). One of the source/drain regions (8a, 8b) of the MOS transistor is connected to a bit line (2a, 2b). The bit line is formed from a contact portion to the source/drain regions of the MOS transistor to a portion above the stacked capacitor. The bit line is formed of a metal having high melting point, a silicide of a metal having high melting point or a polycide. Since this material has low reflectance against exposing light, the precision in patterning the interconnection is improved.

摘要翻译： 半导体存储器件的存储单元包括一个MOS晶体管（3）和一个堆叠电容器（4）。 MOS晶体管的源极/漏极区域（8a，8b）之一连接到位线（2a，2b）。 位线由MOS晶体管的源极/漏极区域到层叠电容器上方的部分的接触部分形成。 位线由具有高熔点的金属，具有高熔点的金属的硅化物或多晶硅化物形成。 由于该材料对于曝光具有低的反射率，因此提高了互连图形化的精度。

公开(公告)号：US5300444A

公开(公告)日：1994-04-05

申请号：US693505

申请日：1991-04-30

申请人： Atsushi Hachisuka ,  Masao Nagatomo ,  Ikuo Ogoh ,  Hideki Genjou ,  Yoshinori Okumura ,  Takayuki Matsukawa

发明人： Atsushi Hachisuka ,  Masao Nagatomo ,  Ikuo Ogoh ,  Hideki Genjou ,  Yoshinori Okumura ,  Takayuki Matsukawa

IPC分类号： H01L21/316 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/265

CPC分类号： H01L27/10844 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/31612 ,  H01L27/10808

摘要： A semiconductor memory device comprising memory cells having stacked capacitors has a stacked structure formed by the selective removal of a polycrystalline silicon film (15; 20) and a silicon oxide film (18a; 18), employing the same mask (14). A field effect transistor connected to a stacked capacitor has a gate electrode (20) formed of the above described polycrystalline silicon film. This polycrystalline silicon film (20) is formed on the major surface of a semiconductor substrate. The above described silicon oxide film (18) as an upper layer insulating film formed on the gate electrode (20) has a residual stress not more than 10.sup.9 dyn/cm.sup.2. No notches occur in the polycrystalline silicon film (20) in the process of selectively removing the polycrystalline silicon film (15) and the silicon oxide film (18a) deposited thereon, employing the same mask (14), thereby not decreasing the operation speed of the field effect transistor having the gate electrode (20) formed of the polycrystalline silicon film.

摘要翻译： 包括具有堆叠电容器的存储单元的半导体存储器件具有通过选择性去除多晶硅膜（15; 20）和使用相同掩模（14）的氧化硅膜（18a; 18）而形成的堆叠结构。 连接到堆叠电容器的场效应晶体管具有由上述多晶硅膜形成的栅电极（20）。 该多晶硅膜（20）形成在半导体衬底的主表面上。 作为形成在栅电极（20）上的上层绝缘膜的上述氧化硅膜（18）的残留应力为109dyn / cm 2以下。 在使用相同的掩模（14）选择性地去除沉积在其上的多晶硅膜（15）和氧化硅膜（18a）的过程中，在多晶硅膜（20）中没有发生缺口，从而不会降低 该场效应晶体管具有由多晶硅膜形成的栅电极（20）。

公开(公告)号：US5231041A

公开(公告)日：1993-07-27

申请号：US819206

申请日：1992-01-10

申请人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

发明人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

IPC分类号： H01L21/8247 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L29/42332 ,  H01L29/7886

摘要： A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layer disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

摘要翻译： 公开了1晶体管型快闪EEPROM。 EEPROM中的存储单元包括形成在硅衬底上的控制栅极，绝缘层设置在它们之间，并且浮置栅极形成为在控制电极的上表面和一个侧面之间设置绝缘层。 在控制栅极的相对侧的硅衬底中产生漏极和源极区。 在漏极和源极区域之间的控制栅极下方的硅衬底中的区域限定沟道区域。 在EEPROM中，向控制栅极和漏极区域施加高电平电压在漏极区域的相对端附近产生热电子，这些电极驱动跨越绝缘层的浮动栅极，从而使浮动栅极 存储数据代表费用。 闪存EEPROM在存储单元之间具有均匀的特性，并且减小了单元面积以改善小型化。

公开(公告)号：US5101250A

公开(公告)日：1992-03-31

申请号：US630439

申请日：1990-12-20

申请人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

发明人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L29/42332 ,  H01L29/7886

摘要： A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layers disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

摘要翻译： 公开了1晶体管型快闪EEPROM。 EEPROM中的存储单元包括形成在硅衬底上的控制栅极，绝缘层位于它们之间，浮栅形成为在控制电极的上表面和一个侧面之间设置绝缘层。 在控制栅极的相对侧的硅衬底中产生漏极和源极区。 在漏极和源极区域之间的控制栅极下方的硅衬底中的区域限定沟道区域。 在EEPROM中，向控制栅极和漏极区域施加高电平电压在漏极区域的相对端附近产生热电子，这些电极驱动跨越绝缘层的浮动栅极，从而使浮动栅极 存储数据代表费用。 闪存EEPROM在存储单元之间具有均匀的特性，并且减小了单元面积以改善小型化。

公开(公告)号：US4956692A

公开(公告)日：1990-09-11

申请号：US266704

申请日：1988-11-03

申请人： Hiroji Ozaki ,  Masahiro Yoneda ,  Ikuo Ogoh ,  Yoshinori Okumura ,  Wataru Wakamiya ,  Masao Nagatomo

发明人： Hiroji Ozaki ,  Masahiro Yoneda ,  Ikuo Ogoh ,  Yoshinori Okumura ,  Wataru Wakamiya ,  Masao Nagatomo

IPC分类号： H01L27/10 ,  H01L21/31 ,  H01L21/334 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L29/66181 ,  H01L21/76205 ,  H01L27/10829

摘要： Two trenches are formed at a predetermined distance on a main surface of a semiconductor substrate. An oxide film and a nitride film are successively formed on the main surface of the semiconductor including the inner surfaces of the trenches. After a resist is formed over the whole surface including the inner surfaces of the trenches, the resist is patterned to expose a portion of the nitride film on a side surface of each trench. The exposed portions of the nitride film are removed by using the patterned resist as a mask and thermal oxidation is applied. Then, an isolation oxide film is formed on a region between the trenches and an end of a bird's beak is located on a side surface of each trench and is connected to the oxide film formed in each trench.

摘要翻译： 在半导体衬底的主表面上以预定距离形成两个沟槽。 在包括沟槽的内表面的半导体的主表面上依次形成氧化物膜和氮化物膜。 在包括沟槽的内表面的整个表面上形成抗蚀剂之后，将抗蚀剂图案化以在每个沟槽的侧表面上暴露出氮化膜的一部分。 通过使用图案化的抗蚀剂作为掩模去除氮化物膜的暴露部分并施加热氧化。 然后，在沟槽之间的区域上形成隔离氧化膜，并且鸟嘴的端部位于每个沟槽的侧表面上并连接到形成在每个沟槽中的氧化膜。

公开(公告)号：US5323343A

公开(公告)日：1994-06-21

申请号：US77971

申请日：1993-06-18

申请人： Ikuo Ogoh ,  Masao Nagatomo

发明人： Ikuo Ogoh ,  Masao Nagatomo

IPC分类号： H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  G11C11/24

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L27/105

摘要： A DRAM according to the present invention comprises a memory cell array having memory cells constituted by one transfer gate transistor (10) and a capacitor (11), and a peripheral circuit having a MOS transistor (45a) with the LDD structure. At least the source/drain region (19) connected to the capacitor of the transfer gate transistor is formed of a low concentration impurity region (19a). The low concentration impurity region has an impurity concentration substantially equal to that of the low concentration source/drain region (31) of the LDD MOS transistor of the peripheral circuit. The low concentration/drain region of the transfer gate transistor is formed by masking the surface thereof at the time of the high concentration ion implantation step for high concentration source/drain formation of the MOS transistor of the peripheral circuit. By omitting the high concentration ion implantation step, the substrate deficiency of the source/drain region of the transfer gate transistor is eliminated to suppress leakage of the charge from the capacitor.

摘要翻译： 根据本发明的DRAM包括具有由一个传输栅极晶体管（10）和电容器（11）构成的存储单元的存储单元阵列和具有LDD结构的MOS晶体管（45a）的外围电路。 至少连接到传输门晶体管的电容器的源极/漏极区域（19）由低浓度杂质区域（19a）形成。 低浓度杂质区域的杂质浓度基本上等于外围电路的LDD MOS晶体管的低浓度源极/漏极区域（31）的杂质浓度。 传输栅极晶体管的低浓度/漏极区域是通过在高浓度离子注入步骤时对其外围电路的MOS晶体管的高浓度源极/漏极形成的表面进行掩蔽来形成的。 通过省略高浓度离子注入步骤，消除了传输栅晶体管的源极/漏极区的衬底缺陷，以抑制电荷从电容器的泄漏。

公开(公告)号：US4905068A

公开(公告)日：1990-02-27

申请号：US143400

申请日：1988-01-13

申请人： Shinichi Satoh ,  Makoto Hirayama ,  Masao Nagatomo ,  Ikuo Ogoh ,  Yoshikazu Ohno ,  Masato Fujinaga

发明人： Shinichi Satoh ,  Makoto Hirayama ,  Masao Nagatomo ,  Ikuo Ogoh ,  Yoshikazu Ohno ,  Masato Fujinaga

IPC分类号： H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/522 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L23/5222 ,  H01L2924/0002

摘要： A cell plate (6) is formed on a main surface of a semiconductor substrate (7) with an insulating film (8) interposed therebetween and an interconnection (1) having T-shape cross section is formed on the cell plate (6) with an interlayer insulating film (11) interposed therebetween. An upper insulating film (12) is formed to cover the interconnection (1).

摘要翻译： 在半导体衬底（7）的主表面上形成有绝缘膜（8）的电池板（6），并且在电池板（6）上形成具有T形横截面的互连（1） 夹在其间的层间绝缘膜（11）。 形成上绝缘膜（12）以覆盖互连（1）。

公开(公告)号：US5075240A

公开(公告)日：1991-12-24

申请号：US509850

申请日：1990-04-17

申请人： Yomiyuki Yama ,  Masatoshi Yasunaga ,  Katsuyoshi Mitsui ,  Ikuo Ogoh

发明人： Yomiyuki Yama ,  Masatoshi Yasunaga ,  Katsuyoshi Mitsui ,  Ikuo Ogoh

IPC分类号： H01L21/265 ,  H01L21/266

CPC分类号： H01L21/266 ,  Y10S438/972

摘要： A conductive resist film is used as a mask in ion implantation. A portion of the conductive resist film is electrically connected to a semiconductor substrate. The charge of ions which enter the conductive resist film in ion implantation flows into the semiconductor substrate and dissipates therein.

摘要翻译： 在离子注入中使用导电抗蚀剂膜作为掩模。 导电抗蚀剂膜的一部分电连接到半导体衬底。 在离子注入中进入导电抗蚀剂膜的离子的电荷流入半导体衬底并在其中消散。

公开(公告)号：US5849616A

公开(公告)日：1998-12-15

申请号：US770204

申请日：1996-12-19

申请人： Ikuo Ogoh

发明人： Ikuo Ogoh

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/6659 ,  H01L21/823864 ,  H01L27/0922 ,  H01L29/6656 ,  H01L29/66659 ,  Y10S257/90

摘要： A semiconductor device comprises a semiconductor substrate (11) having first and second field effect transistors. Each transistor includes a gate electrode (17, 18) formed on the semiconductor substrate with a gate insulating film (15, 16) interposed therebetween. A first side wall spacer (21, 22) formed of one layer of an insulating film on opposite side wall surface of the gate electrode, and source/drain regions (19, 24, 26, 30), each comprising high and/or low impurity concentration regions of the gate electrode (17, 18) on the surface of the semiconductor substrate (11). A second side wall spacer (27, 28) formed of another layer of an insulating film formed at least one side wall surface of the gate electrode (17, 18) of at least said second transistor. The first and/or the second side wall spacers (21, 22, 27, 28) form diffusion masks for adjusting distribution of impurity concentration of the transistors. Due to this structure, the widths of the side wall spacers (21, 22, 27, 28) as diffusion masks which are responsive to required characteristics, are attained for respective side walls of the gate electrodes (17, 18). The semiconductor device of such structure is manufacutred by implanting impurity ions between the steps of forming the first and the second side wall spacers (21, 22, 27, 28) and each time covering prescribed region with a resist film (20, 23, 25, 29, 31, 33, 35).

摘要翻译： 半导体器件包括具有第一和第二场效应晶体管的半导体衬底（11）。 每个晶体管包括形成在半导体衬底上的栅电极（17,18），其间插入有栅极绝缘膜（15,16）。 由栅电极的相对侧壁表面上的一层绝缘膜形成的第一侧壁间隔物（21,22）和源极/漏极区（19,24,26,30），每个包括高和/或低 在半导体衬底（11）的表面上的栅电极（17,18）的杂质浓度区域。 由形成至少所述第二晶体管的栅电极（17,18）的至少一个侧壁表面的绝缘膜的另一层形成的第二侧壁间隔物（27,28）。 第一和/或第二侧壁间隔物（21,22,27,28）形成用于调节晶体管的杂质浓度分布的扩散掩模。 由于这种结构，对于栅电极（17,18）的各个侧壁，获得作为响应所需特性的扩散掩模的侧壁间隔物（21,22,27,28）的宽度。 这种结构的半导体器件通过在形成第一和第二侧壁间隔物（21,22,27,28）的步骤之间注入杂质离子并且每次用抗蚀剂膜（20,23,25）覆盖规定区域来制造 ，29,31,33,35）。

公开(公告)号：US5547885A

公开(公告)日：1996-08-20

申请号：US462938

申请日：1995-06-02

申请人： Ikuo Ogoh

发明人： Ikuo Ogoh

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234

CPC分类号： H01L29/6659 ,  H01L21/823864 ,  H01L27/0922 ,  H01L29/6656 ,  H01L29/66659 ,  Y10S257/90

摘要： A semiconductor device comprises a semiconductor substrate (11) having first and second field effect transistors. Each transistor includes a gate electrode (17, 18) formed on the semiconductor substrate with a gate insulating film (15, 16) interposed therebetween. A first side wall spacer (21, 22) formed of one layer of an insulating film on opposite side wall surface of the gate electrode, and source/drain regions (19, 24, 26, 30), each comprising high and/or low impurity concentration regions of the gate electrode (17, 18) on the surface of the semiconductor substrate (11). A second side wall spacer (27, 28) formed of another layer of an insulating film formed at least one side wall surface of the gate electrode (17, 18) of at least said second transistor. The first and/or the second side wall spacers (21, 22, 27, 28) form diffusion masks for adjusting distribution of impurity concentration of the transistors. Due to this structure, the widths of the side wall spacers (21, 22, 27, 28) as diffusion masks which are responsive to required characteristics, are attained for respective side walls of the gate electrodes (17, 18). The semiconductor device of such structure is manufactured by implanting impurity ions between the steps of forming the first and the second side wall spacers (21, 22, 27, 28) and each time covering prescribed region with a resist film (20, 23, 25, 29, 31, 33, 35).

摘要翻译： 半导体器件包括具有第一和第二场效应晶体管的半导体衬底（11）。 每个晶体管包括形成在半导体衬底上的栅电极（17,18），其间插入有栅极绝缘膜（15,16）。 由栅电极的相对侧壁表面上的一层绝缘膜形成的第一侧壁间隔物（21,22）和源极/漏极区（19,24,26,30），每个包括高和/或低 在半导体衬底（11）的表面上的栅电极（17,18）的杂质浓度区域。 由形成至少所述第二晶体管的栅电极（17,18）的至少一个侧壁表面的绝缘膜的另一层形成的第二侧壁间隔物（27,28）。 第一和/或第二侧壁间隔物（21,22,27,28）形成用于调节晶体管的杂质浓度分布的扩散掩模。 由于这种结构，对于栅电极（17,18）的各个侧壁，获得作为响应所需特性的扩散掩模的侧壁间隔物（21,22,27,28）的宽度。 这种结构的半导体器件通过在形成第一和第二侧壁间隔物（21,22,27,28）的步骤之间注入杂质离子并且每次用抗蚀剂膜（20,23,25）覆盖规定的区域来制造 ，29,31,33,35）。