公开(公告)号：US5153689A

公开(公告)日：1992-10-06

申请号：US404528

申请日：1989-09-08

申请人： Yoshinori Okumura ,  Takayuki Matsukawa ,  Ikuo Ogoh ,  Masao Nagatomo ,  Hideki Genjo ,  Atsushi Hachisuka

发明人： Yoshinori Okumura ,  Takayuki Matsukawa ,  Ikuo Ogoh ,  Masao Nagatomo ,  Hideki Genjo ,  Atsushi Hachisuka

IPC分类号： H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/532 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10808 ,  H01L23/53257 ,  H01L2924/0002

摘要： A memory cell of a semiconductor memory device comprises one MOS transistor (3) and one stacked capacitor (4). One of the source/drain regions (8a, 8b) of the MOS transistor is connected to a bit line (2a, 2b). The bit line is formed from a contact portion to the source/drain regions of the MOS transistor to a portion above the stacked capacitor. The bit line is formed of a metal having high melting point, a silicide of a metal having high melting point or a polycide. Since this material has low reflectance against exposing light, the precision in patterning the interconnection is improved.

摘要翻译： 半导体存储器件的存储单元包括一个MOS晶体管（3）和一个堆叠电容器（4）。 MOS晶体管的源极/漏极区域（8a，8b）之一连接到位线（2a，2b）。 位线由MOS晶体管的源极/漏极区域到层叠电容器上方的部分的接触部分形成。 位线由具有高熔点的金属，具有高熔点的金属的硅化物或多晶硅化物形成。 由于该材料对于曝光具有低的反射率，因此提高了互连图形化的精度。

公开(公告)号：US5300444A

公开(公告)日：1994-04-05

申请号：US693505

申请日：1991-04-30

申请人： Atsushi Hachisuka ,  Masao Nagatomo ,  Ikuo Ogoh ,  Hideki Genjou ,  Yoshinori Okumura ,  Takayuki Matsukawa

发明人： Atsushi Hachisuka ,  Masao Nagatomo ,  Ikuo Ogoh ,  Hideki Genjou ,  Yoshinori Okumura ,  Takayuki Matsukawa

IPC分类号： H01L21/316 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/265

CPC分类号： H01L27/10844 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/31612 ,  H01L27/10808

摘要： A semiconductor memory device comprising memory cells having stacked capacitors has a stacked structure formed by the selective removal of a polycrystalline silicon film (15; 20) and a silicon oxide film (18a; 18), employing the same mask (14). A field effect transistor connected to a stacked capacitor has a gate electrode (20) formed of the above described polycrystalline silicon film. This polycrystalline silicon film (20) is formed on the major surface of a semiconductor substrate. The above described silicon oxide film (18) as an upper layer insulating film formed on the gate electrode (20) has a residual stress not more than 10.sup.9 dyn/cm.sup.2. No notches occur in the polycrystalline silicon film (20) in the process of selectively removing the polycrystalline silicon film (15) and the silicon oxide film (18a) deposited thereon, employing the same mask (14), thereby not decreasing the operation speed of the field effect transistor having the gate electrode (20) formed of the polycrystalline silicon film.

摘要翻译： 包括具有堆叠电容器的存储单元的半导体存储器件具有通过选择性去除多晶硅膜（15; 20）和使用相同掩模（14）的氧化硅膜（18a; 18）而形成的堆叠结构。 连接到堆叠电容器的场效应晶体管具有由上述多晶硅膜形成的栅电极（20）。 该多晶硅膜（20）形成在半导体衬底的主表面上。 作为形成在栅电极（20）上的上层绝缘膜的上述氧化硅膜（18）的残留应力为109dyn / cm 2以下。 在使用相同的掩模（14）选择性地去除沉积在其上的多晶硅膜（15）和氧化硅膜（18a）的过程中，在多晶硅膜（20）中没有发生缺口，从而不会降低 该场效应晶体管具有由多晶硅膜形成的栅电极（20）。

公开(公告)号：US5231041A

公开(公告)日：1993-07-27

申请号：US819206

申请日：1992-01-10

申请人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

发明人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

IPC分类号： H01L21/8247 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L29/42332 ,  H01L29/7886

摘要： A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layer disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

摘要翻译： 公开了1晶体管型快闪EEPROM。 EEPROM中的存储单元包括形成在硅衬底上的控制栅极，绝缘层设置在它们之间，并且浮置栅极形成为在控制电极的上表面和一个侧面之间设置绝缘层。 在控制栅极的相对侧的硅衬底中产生漏极和源极区。 在漏极和源极区域之间的控制栅极下方的硅衬底中的区域限定沟道区域。 在EEPROM中，向控制栅极和漏极区域施加高电平电压在漏极区域的相对端附近产生热电子，这些电极驱动跨越绝缘层的浮动栅极，从而使浮动栅极 存储数据代表费用。 闪存EEPROM在存储单元之间具有均匀的特性，并且减小了单元面积以改善小型化。

公开(公告)号：US5101250A

公开(公告)日：1992-03-31

申请号：US630439

申请日：1990-12-20

申请人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

发明人： Hideaki Arima ,  Yoshinori Okumura ,  Hideki Genjo ,  Ikuo Ogoh ,  Kohjiroh Yuzuriha ,  Yuichi Nakashima

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L29/42332 ,  H01L29/7886

摘要： A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layers disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

摘要翻译： 公开了1晶体管型快闪EEPROM。 EEPROM中的存储单元包括形成在硅衬底上的控制栅极，绝缘层位于它们之间，浮栅形成为在控制电极的上表面和一个侧面之间设置绝缘层。 在控制栅极的相对侧的硅衬底中产生漏极和源极区。 在漏极和源极区域之间的控制栅极下方的硅衬底中的区域限定沟道区域。 在EEPROM中，向控制栅极和漏极区域施加高电平电压在漏极区域的相对端附近产生热电子，这些电极驱动跨越绝缘层的浮动栅极，从而使浮动栅极 存储数据代表费用。 闪存EEPROM在存储单元之间具有均匀的特性，并且减小了单元面积以改善小型化。

公开(公告)号：US4956692A

公开(公告)日：1990-09-11

申请号：US266704

申请日：1988-11-03

申请人： Hiroji Ozaki ,  Masahiro Yoneda ,  Ikuo Ogoh ,  Yoshinori Okumura ,  Wataru Wakamiya ,  Masao Nagatomo

发明人： Hiroji Ozaki ,  Masahiro Yoneda ,  Ikuo Ogoh ,  Yoshinori Okumura ,  Wataru Wakamiya ,  Masao Nagatomo

IPC分类号： H01L27/10 ,  H01L21/31 ,  H01L21/334 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L29/66181 ,  H01L21/76205 ,  H01L27/10829

摘要： Two trenches are formed at a predetermined distance on a main surface of a semiconductor substrate. An oxide film and a nitride film are successively formed on the main surface of the semiconductor including the inner surfaces of the trenches. After a resist is formed over the whole surface including the inner surfaces of the trenches, the resist is patterned to expose a portion of the nitride film on a side surface of each trench. The exposed portions of the nitride film are removed by using the patterned resist as a mask and thermal oxidation is applied. Then, an isolation oxide film is formed on a region between the trenches and an end of a bird's beak is located on a side surface of each trench and is connected to the oxide film formed in each trench.

摘要翻译： 在半导体衬底的主表面上以预定距离形成两个沟槽。 在包括沟槽的内表面的半导体的主表面上依次形成氧化物膜和氮化物膜。 在包括沟槽的内表面的整个表面上形成抗蚀剂之后，将抗蚀剂图案化以在每个沟槽的侧表面上暴露出氮化膜的一部分。 通过使用图案化的抗蚀剂作为掩模去除氮化物膜的暴露部分并施加热氧化。 然后，在沟槽之间的区域上形成隔离氧化膜，并且鸟嘴的端部位于每个沟槽的侧表面上并连接到形成在每个沟槽中的氧化膜。

公开(公告)号：US4984055A

公开(公告)日：1991-01-08

申请号：US267103

申请日：1988-11-07

申请人： Yoshinori Okumura ,  Atsuhiro Fujii ,  Masao Nagatomo ,  Hiroji Ozaki ,  Wataru Wakamiya ,  Takayuki Matsukawa

发明人： Yoshinori Okumura ,  Atsuhiro Fujii ,  Masao Nagatomo ,  Hiroji Ozaki ,  Wataru Wakamiya ,  Takayuki Matsukawa

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/522 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L23/485 ,  H01L23/522 ,  H01L2924/0002

摘要： A semiconductor device having a plurality of conductive layers is disclosed. The device has first level conductors (9) formed spaced apart on a semiconductor substrate (1). The semiconductor substrate (1) is provided with impurity diffusion regions (11) in its major surface between adjacent first level conductors (9). A triple layer insulation formed of a pair of oxide layers (12, 14) and an silicon oxide layer (13) sandwiched between the oxide layers (12, 14) covers the semiconductor substrate (1) and the first level conductors (9) thereon. At least one contact hole (15) is formed to extend through the triple layer insulation to either the impurity diffusion region (11) in the semiconductor substrate (1) or the first level conductor (9) on the semiconductor substrate (1). A second level conductor (16, 17) is provided on the triple layer insulation and on the inner surrounding wall of the contact hole (15). Each of the three insulating layers in the triple layer insulation has its hole-defining surface exposed at the contact hole (15) flush with or displaced laterally into the contact hole (15) away from a corresponding hole-defining exposed surface of the next overlying insulating layer.

摘要翻译： 公开了具有多个导电层的半导体器件。 该器件具有在半导体衬底（1）上间隔开形成的第一级导体（9）。 半导体衬底（1）在相邻的第一层导体（9）之间的主表面上设置有杂质扩散区（11）。 由一对氧化物层（12,14）和夹在氧化物层（12,14）之间的氧化硅层（13）形成的三层绝缘体覆盖在其上的半导体衬底（1）和第一层导体（9） 。 形成至少一个接触孔（15），以通过三层绝缘体延伸到半导体衬底（1）中的杂质扩散区域（11）或半导体衬底（1）上的第一级导体（9）中。 在三层绝缘体和接触孔（15）的内周围壁上设置有二级导体（16,17）。 三层绝缘体中的三个绝缘层中的每一个具有其露出在接触孔（15）处的孔限定表面，该接触孔（15）与接触孔（15）平齐地或相对地偏离接触孔（15），远离与下一个上覆的相应的孔限定的暴露表面 绝缘层。

公开(公告)号：US5502324A

公开(公告)日：1996-03-26

申请号：US363548

申请日：1994-12-23

申请人： Atsushi Hachisuka ,  Yoshinori Okumura

发明人： Atsushi Hachisuka ,  Yoshinori Okumura

IPC分类号： H01L23/52 ,  H01L21/28 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/532 ,  H01L27/06 ,  H01L27/10 ,  H01L27/108 ,  H01L29/43 ,  H01L29/49 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L21/76897 ,  H01L21/76889 ,  H01L23/485 ,  H01L23/53271 ,  H01L27/10873 ,  H01L29/4983 ,  H01L2924/0002

摘要： An electrode wiring layer of a semiconductor device according to this invention includes a first conductive portion formed of polycrystalline silicon or the like, and second conductive portions formed as refractory metal silicide layers on opposite lateral walls of the first conductive portion. Upper surfaces and lateral surfaces thereof are coated with insulating layers formed in separate processes. The insulating layers covering the lateral surfaces in particular are formed by a self-aligning technique requiring no mask process. Where conductive layers are formed over the wiring layer according to this invention, a film forming and patterning process for insulating the conductive portions of the wiring layer is omitted and insulation of the wiring layer is secured.

摘要翻译： 根据本发明的半导体器件的电极布线层包括由多晶硅等形成的第一导电部分和在第一导电部分的相对侧壁上形成为难熔金属硅化物层的第二导电部分。 其上表面和侧表面涂覆有分离工艺形成的绝缘层。 覆盖侧表面的绝缘层特别地由不需要掩模处理的自对准技术形成。 在根据本发明的布线层上形成导电层的情况下，省略了用于绝缘布线层的导电部分的成膜和图案化工艺，并且确保了布线层的绝缘。

公开(公告)号：US5281838A

公开(公告)日：1994-01-25

申请号：US899021

申请日：1992-06-15

申请人： Yoshinori Okumura ,  Atsushi Hachisuka

发明人： Yoshinori Okumura ,  Atsushi Hachisuka

IPC分类号： H01L23/485 ,  H01L27/108 ,  H01L23/48 ,  H01L29/46 ,  H01L29/54

CPC分类号： H01L23/485 ,  H01L27/10805 ,  H01L2924/0002

摘要： A semiconductor device is disclosed that can form contacts with ease even if the distance between adjacent gate electrodes is reduced in accordance with larger scale integration of semiconductor devices. The semiconductor device includes a polysilicon pad 8c connected to impurity implanted layers 5a and 7a, formed over sidewalls 6a and 6b of gate electrodes 3a and 3b and insulating films 4a and 4b; and a polysilicon pad 11a connected to impurity implanted layers 5b and 7b, formed over polysilicon pad 8c with an insulating film 9 and sidewalls 10b therebetween. Even if elements are miniaturized to have reduced gate electrode length and gate electrode distance in accordance with larger scale integration of a semiconductor device, polysilicon pads 8c and 11a can be formed with ease between impurity implanted layers 5a, 7a and an upper layer wiring 13a, and between impurity implanted layers 5b, 7b and an upper layer wiring 13b, respectively. Thus, contact holes 15a and 15b can be formed without difficulty for forming upper layer wirings 13a and 13b, even if semiconductor devices are increased to larger scale integration.

摘要翻译： 公开了一种能够容易地形成接触的半导体器件，即使根据半导体器件的大规模集成，相邻栅电极之间的距离减小。 半导体器件包括连接到杂质注入层5a和7a的多晶硅焊盘8c，其形成在栅电极3a和3b的侧壁6a和6b以及绝缘膜4a和4b上; 以及与杂质注入层5b和7b连接的多晶硅焊盘11a，其形成在多晶硅焊盘8c的绝缘膜9和它们之间的侧壁10b之间。 即使元件小型化以根据半导体器件的大规模集成来减小栅极电极长度和栅极电极距离，可以容易地在杂质注入层5a，7a和上层布线13a之间形成多晶硅焊盘8c和11a， 以及杂质注入层5b，7b和上层布线13b之间。 因此，即使半导体器件增加到更大规模的集成，也可以形成上层配线13a，13b难以形成接触孔15a，15b。

公开(公告)号：US4985368A

公开(公告)日：1991-01-15

申请号：US429528

申请日：1989-10-31

申请人： Tatsuya Ishii ,  Yoshinori Okumura ,  Masao Nagatomo

发明人： Tatsuya Ishii ,  Yoshinori Okumura ,  Masao Nagatomo

IPC分类号： H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10861 ,  H01L27/10829 ,  H01L29/66181 ,  Y10S257/911

摘要： The semiconductor device in which no stress occurs at the corner portion of the trench comprises a p type semiconductor substrate having a trench and a main surface, a thick insulating film formed on the bottom portion of the trench, a thin insulating film formed on the sidewall portion of the trench and connected to the end portion of the thick insulating film, and an n type impurity region formed in the semiconductor substrate only on the side portion of the thin insulating film.

公开(公告)号：US4894695A

公开(公告)日：1990-01-16

申请号：US169062

申请日：1988-03-17

申请人： Tatsuya Ishii ,  Yoshinori Okumura ,  Masao Nagatomo

发明人： Tatsuya Ishii ,  Yoshinori Okumura ,  Masao Nagatomo

IPC分类号： H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10861 ,  H01L27/10829 ,  H01L29/66181 ,  Y10S257/911

摘要： The semiconductor device in which no stress occurs at the corner portion of the trench comprises a p type semiconductor substrate having a trench and a main surface, a thick insulating film formed on the bottom portion of the trench, a thin insulating film formed on the sidewall portion of the trench and connected to the end portion of the thick insulating film, and an n type impurity region formed in the semiconductor substrate only on the side portion of the thin insulating film.

摘要翻译： 在沟槽的角部没有发生应力的半导体器件包括具有沟槽和主表面的ap型半导体衬底，形成在沟槽底部的厚绝缘膜，形成在侧壁部分上的薄绝缘膜 并且连接到厚绝缘膜的端部，并且仅在薄绝缘膜的侧部形成在半导体衬底中的n型杂质区。