公开(公告)号：US4767516A

公开(公告)日：1988-08-30

申请号：US864357

申请日：1986-05-19

申请人： Yoshio Nakatsuka ,  Minoru Kume ,  Daisuke Kishimoto

发明人： Yoshio Nakatsuka ,  Minoru Kume ,  Daisuke Kishimoto

IPC分类号： G11B5/851 ,  C23C14/36

CPC分类号： G11B5/851

摘要： A magnetic recording tape making process and apparatus is disclosed. The apparatus includes a first depositing station which utilizes a the sputtering process for depositing a seed layer on a substrate with an initial incident angle of about 5.degree., and a second depositing station for depositing, over the seed layer, an extended layer with an initial incident angle of about 45.degree.. The seed layer has a thickness of about 0.01 micrometer, and is defined by young crystalline columns of magnetic material densely and perpendicularly formed on the substrate. The extended layer is defined by extended crystalline columns over the young crystalline columns through self-epitaxial growth. The completed magnetic film defined by the two layers has a high residual magnetization ratio MV/MH and also a high perpendicular coercivity Hcv.

摘要翻译： 公开了一种磁记录带制造工艺和装置。 该装置包括第一沉积站，其利用溅射工艺在基板上沉积约5°的初始入射角;以及第二沉积站，用于在种子层上沉积具有初始 入射角约45°。 种子层具有约0.01微米的厚度，并且由基底上密集且垂直形成的磁性材料的年轻晶体层限定。 扩展层由延伸的结晶柱通过自外延生长在年轻的结晶柱上限定。 由两层限定的完成的磁性膜具有高残留磁化比MV / MH，并且还具有高垂直矫顽力Hcv。

公开(公告)号：US5715358A

公开(公告)日：1998-02-03

申请号：US742325

申请日：1996-11-01

申请人： Takashi Ohnaka ,  Katsuhiko Matsushita ,  Daisuke Kishimoto ,  Minoru Takahashi ,  Minoru Kume ,  Mitsutaka Komoike ,  Katsunori Hirase ,  Tatsuo Tanaka ,  Hirotsugu Murashima ,  Osamu Idegata ,  Masafumi Nishi

发明人： Takashi Ohnaka ,  Katsuhiko Matsushita ,  Daisuke Kishimoto ,  Minoru Takahashi ,  Minoru Kume ,  Mitsutaka Komoike ,  Katsunori Hirase ,  Tatsuo Tanaka ,  Hirotsugu Murashima ,  Osamu Idegata ,  Masafumi Nishi

IPC分类号： H04N5/7822 ,  H04N5/7826 ,  H04N9/79 ,  H04N9/797 ,  H04N9/804 ,  H04N9/82 ,  H04N9/83 ,  H04N13/00 ,  H04N5/76

CPC分类号： H04N13/0055 ,  H04N13/0048 ,  H04N19/597 ,  H04N9/8227 ,  H04N13/0051 ,  H04N13/0059 ,  H04N5/7822 ,  H04N5/78263 ,  H04N9/7904 ,  H04N9/7973 ,  H04N9/8047 ,  H04N9/83

摘要： In the event of recording a picture signal for left eye and a picture signal for right eye, a picture signal for one of right and left eyes limited in band by a low pass filter as being an additional signal and a picture signal for the other eye as being a primary signal, and the additional signal together with the primary signal are recorded on recording medium.

摘要翻译： 在记录左眼用图像信号和右眼用图像信号的情况下，由低通滤波器限制的右眼和左眼中的一只眼睛的图像信号作为附加信号，另一只眼睛的图像信号 作为主信号，并且附加信号与主信号一起被记录在记录介质上。

公开(公告)号：US07821014B2

公开(公告)日：2010-10-26

申请号：US11683993

申请日：2007-03-08

申请人： Yoshiyuki Yonezawa ,  Daisuke Kishimoto

发明人： Yoshiyuki Yonezawa ,  Daisuke Kishimoto

IPC分类号： H01L31/0312 ,  H01L29/06 ,  H01L21/332 ,  H01L21/8222

CPC分类号： H01L29/66068 ,  H01L21/0465 ,  H01L29/7827

摘要： A semiconductor device and a manufacturing method thereof uses a semiconductor substrate of silicon carbide. On one principal surface side of the substrate, at its central section, a layer of silicon carbide or gallium nitride as a semiconductor layer having the thickness at least necessary for breakdown voltage blocking is epitaxially grown or formed from part of the substrate. A recess is formed in the other principal surface side of substrate at a position facing the central section. A supporting section surrounds the bottom of the recess and provides the side face of the recess. The recess is formed by processing such as dry etching. The semiconductor device, even though the semiconductor substrate is made thinner for the realization of small on-resistance, can maintain the strength of the semiconductor substrate capable of reducing occurrence of a wafer cracking during the manufacturing process.

摘要翻译： 半导体器件及其制造方法使用碳化硅的半导体衬底。 在衬底的一个主表面上，在其中心部分，由衬底的一部分外延生长或形成具有至少为击穿电压阻挡所必需的厚度的半导体层的碳化硅或氮化镓层。 在面向中心部的位置的基板的另一主面侧形成有凹部。 支撑部分围绕凹部的底部并且提供凹部的侧面。 凹部通过诸如干法蚀刻的处理形成。 半导体器件即使半导体衬底被制成较薄以实现小的导通电阻，也可以在制造过程中保持能够减少晶片开裂发生的半导体衬底的强度。

公开(公告)号：US20060154438A1

公开(公告)日：2006-07-13

申请号：US11233377

申请日：2005-09-23

申请人： Daisuke Kishimoto ,  Hitoshi Kuribayashi ,  Yuji Sano ,  Akihiko Ohi ,  Yoshihiko Nagayasu

发明人： Daisuke Kishimoto ,  Hitoshi Kuribayashi ,  Yuji Sano ,  Akihiko Ohi ,  Yoshihiko Nagayasu

IPC分类号： H01L21/76 ,  H01L21/302

CPC分类号： H01L29/7813 ,  H01L21/02057 ,  H01L21/3065 ,  H01L21/3247 ,  H01L21/76248 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/513 ,  H01L29/66734

摘要： In the method for manufacturing a semiconductor device according to the invention including the step of forming trenches having the depth thereof in perpendicular to the major surface of a semiconductor substrate, the step of forming trenches includes the steps of performing trench etching using an insulator film, formed on the major surface of the semiconductor substrate and shaped with a predetermined pattern, for a mask to form the trenches; etching the inside of the trenches using a halogen containing gas to smoothen the inside of the trenches; and thermally treating in a non-oxidizing and non-nitriding atmosphere. The manufacturing method according to the invention facilitates well removing the etching residues remaining in the trenches and rounding the trench corners properly when the trenches are 2 μm or narrower in width and even when the trenches are 1 μm or narrower in width.

摘要翻译： 在根据本发明的半导体器件的制造方法中，包括形成其深度与半导体衬底的主表面垂直的沟槽的步骤，形成沟槽的步骤包括以下步骤：使用绝缘膜进行沟槽蚀刻， 形成在半导体衬底的主表面上并以预定图案成形，用于掩模以形成沟槽; 使用含卤素气体蚀刻沟槽的内部以平滑沟槽的内部; 并在非氧化和非氮化气氛中进行热处理。 根据本发明的制造方法有助于很好地去除残留在沟槽中的蚀刻残留物，并且当沟槽为2μm或宽度较窄时，甚至当沟槽为1μm或宽度较窄时，恰当地对沟槽角进行四舍五入。

公开(公告)号：US20060252243A1

公开(公告)日：2006-11-09

申请号：US11398659

申请日：2006-04-06

申请人： Daisuke Kishimoto ,  Takeshi Tawara ,  Shunsuke Izumi

发明人： Daisuke Kishimoto ,  Takeshi Tawara ,  Shunsuke Izumi

IPC分类号： H01L21/44 ,  H01L21/76

CPC分类号： H01L21/02378 ,  C30B25/12 ,  C30B25/14 ,  H01L21/02529 ,  H01L21/0262

摘要： An epitaxial film deposition system includes a reactor, a susceptor, a wafer heating unit, a reactant gas supply orifice, and an aperture for venting the reactant gas. The reactant gas is supplied to a reactor region between the susceptor and a graphite plate so as to circulate in layered flow in a direction along the reactor inner wall in the planar direction of a mounted SiC wafer. The temperature of the wafer is controlled by a high frequency coil and halogen lamps based on temperatures detected by a pyrometer. By circulating the reactant gas over the surface of the stationary wafer, it is possible to form, under various process conditions, an SiC epitaxial film having good film quality and good uniformity of film thickness, without providing any wafer rotation mechanism.

摘要翻译： 外延膜沉积系统包括反应器，基座，晶片加热单元，反应气体供应孔和用于排出反应气体的孔。 将反应气体供给到基座和石墨板之间的反应器区域，以便在安装的SiC晶片的平面方向上沿着反应器内壁的方向以分层流动循环。 基于由高温计检测的温度，由高频线圈和卤素灯控制晶片的温度。 通过将反应气体循环在固定晶片的表面上，可以在各种工艺条件下形成具有良好的膜质量和良好的膜厚均匀性的SiC外延膜，而不需要提供任何晶片旋转机构。

公开(公告)号：US07029977B2

公开(公告)日：2006-04-18

申请号：US10792884

申请日：2004-03-05

申请人： Daisuke Kishimoto ,  Susumu Iwamoto ,  Katsunori Ueno ,  Ryohsuke Shimizu ,  Satoshi Oka

发明人： Daisuke Kishimoto ,  Susumu Iwamoto ,  Katsunori Ueno ,  Ryohsuke Shimizu ,  Satoshi Oka

IPC分类号： H01L21/336 ,  H01L21/4763

CPC分类号： H01L29/0634 ,  C30B25/18 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0688

摘要： A fabrication method of a semiconductor wafer can fill trenches formed in a semiconductor substrate with an epitaxial film with high crystal quality without leaving cavities in the trenches. The trenches are formed in the first conductivity type semiconductor substrate. Planes exposed inside the trenches are made clean surfaces by placing the substrate in a gas furnace, followed by supplying the furnace with an etching gas and carrier gas, and by performing etching on the exposed planes inside the trenches by a thickness from about a few nanometers to one micrometer. The trenches have a geometry opening upward through the etching. Following the etching, a second conductivity type semiconductor is epitaxially grown in the trenches by supplying the furnace with a growth gas, etching gas, doping gas and carrier gas, thereby filling the trenches. Instead of making the trenches slightly-opened upward, their sidewalls may be made planes enabling facet formation.

摘要翻译： 半导体晶片的制造方法可以用具有高晶体质量的外延膜填充在半导体衬底中形成的沟槽，而不会在沟槽中留下空洞。 沟槽形成在第一导电型半导体衬底中。 通过将衬底放置在气体炉中，然后向炉内供应蚀刻气体和载气，并且通过在沟槽内的暴露平面上蚀刻约几纳米的厚度，将暴露在沟槽内的平面制成干净的表面 至一微米。 沟槽具有通过蚀刻向上的几何形状。 在蚀刻之后，通过向炉提供生长气体，蚀刻气体，掺杂气体和载气，从而在沟槽中外延生长第二导电型半导体，由此填充沟槽。 不是使沟槽向上略微打开，它们的侧壁可以制成使得能够形成小平面的平面。

公开(公告)号：US07510975B2

公开(公告)日：2009-03-31

申请号：US11233377

申请日：2005-09-23

申请人： Daisuke Kishimoto ,  Hitoshi Kuribayashi ,  Yuji Sano ,  Akihiko Ohi ,  Yoshihiko Nagayasu

发明人： Daisuke Kishimoto ,  Hitoshi Kuribayashi ,  Yuji Sano ,  Akihiko Ohi ,  Yoshihiko Nagayasu

IPC分类号： H01L21/302

CPC分类号： H01L29/7813 ,  H01L21/02057 ,  H01L21/3065 ,  H01L21/3247 ,  H01L21/76248 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/513 ,  H01L29/66734

摘要： In the method for manufacturing a semiconductor device according to the invention including the step of forming trenches having the depth thereof in perpendicular to the major surface of a semiconductor substrate, the step of forming trenches includes the steps of performing trench etching using an insulator film, formed on the major surface of the semiconductor substrate and shaped with a predetermined pattern, for a mask to form the trenches; etching the inside of the trenches using a halogen containing gas to smoothen the inside of the trenches; and thermally treating in a non-oxidizing and non-nitriding atmosphere. The manufacturing method according to the invention facilitates well removing the etching residues remaining in the trenches and rounding the trench corners properly when the trenches are 2 μm or narrower in width and even when the trenches are 1 μm or narrower in width.

摘要翻译： 在根据本发明的半导体器件的制造方法中，包括形成其深度与半导体衬底的主表面垂直的沟槽的步骤，形成沟槽的步骤包括以下步骤：使用绝缘膜进行沟槽蚀刻， 形成在半导体衬底的主表面上并以预定图案成形，用于掩模以形成沟槽; 使用含卤素气体蚀刻沟槽的内部以平滑沟槽的内部; 并在非氧化和非氮化气氛中进行热处理。 根据本发明的制造方法有助于很好地去除残留在沟槽中的蚀刻残留物，并且当沟槽为2μm或宽度较窄时，甚至当沟槽为1μm或宽度较窄时，恰当地对沟槽角进行四舍五入。

公开(公告)号：US07355257B2

公开(公告)日：2008-04-08

申请号：US11370188

申请日：2006-03-08

申请人： Daisuke Kishimoto ,  Susumu Iwamoto ,  Katsunori Ueno

发明人： Daisuke Kishimoto ,  Susumu Iwamoto ,  Katsunori Ueno

IPC分类号： H01L31/00 ,  H01L23/58

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/157 ,  H01L29/7813 ,  H01L29/7825 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor superjunction device has a superjunction structure formed in a drift region of the device. The superjunction structure has alternately arranged n-type regions and p-type semiconductor regions layered parallel with the drift direction of carriers, permitting current flow when turned ON and depleting when turned OFF. It also includes a first intrinsic semiconductor region between the n-type and p-type regions. The first intrinsic semiconductor region and the n-type and p-type regions sandwiching the first intrinsic semiconductor region forming a unit. A plurality of units are repetitively arranged to form a repetitively arranged structure. The value of mobility of one of electrons in the n-type region or holes in the p-type region is equal to or less than half the value of mobility of corresponding to one of electrons or holes in the first intrinsic semiconductor region. The superjunction structure eliminates the lower limit that prevents further narrowing of the widths of the n-type and p-type regions to further improve the tradeoff relationship between increasing the breakdown voltage and reducing the on-resistance.

摘要翻译： 半导体超结装置具有形成在装置的漂移区域中的超结构结构。 超结构结构交替布置与载流子漂移方向平行分布的n型区域和p型半导体区域，当导通时允许电流流动并且在关断时耗尽。 它还包括n型和p型区之间的第一本征半导体区。 第一本征半导体区域和夹着形成单元的第一本征半导体区域的n型和p型区域。 重复地布置多个单元以形成重复排列的结构。 n型区域中的电子之一或p型区域中的空穴的迁移率的值等于或小于对应于第一本征半导体区域中的电子或空穴之一的迁移率的值的一半。 超结结构消除了阻止n型和p型区域的宽度进一步变窄的下限，以进一步提高增加击穿电压和降低导通电阻之间的折衷关系。

公开(公告)号：US20070015333A1

公开(公告)日：2007-01-18

申请号：US11452053

申请日：2006-06-13

申请人： Daisuke Kishimoto ,  Takeshi Tawara ,  Takashi Tsuji ,  Shunsuke Izumi

发明人： Daisuke Kishimoto ,  Takeshi Tawara ,  Takashi Tsuji ,  Shunsuke Izumi

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/02057 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/66068

摘要： A method of manufacturing a semiconductor device is disclosed that includes the treating the surface of a SiC semiconductor substrate prior to forming a gate oxide film on the SiC semiconductor substrate in order to etch the SiC semiconductor substrate by several nm to 0.1 μm with hydrogen in a reaction furnace. The treating is conducted a reduced pressure in the furnace, at a temperature of 1500° C. or higher. The manufacturing method facilitates the removal of particles and oxide residues remaining on the trench inner wall after trench etching in the manufacturing process for manufacturing a SiC semiconductor device having a fine trench-type MOS gate structure.

摘要翻译： 公开了一种制造半导体器件的方法，其包括在SiC半导体衬底上形成栅极氧化膜之前处理SiC半导体衬底的表面，以便将SiC半导体衬底在 反应炉。 在1500℃以上的温度下，在炉内进行减压处理。 在制造具有细沟槽型MOS栅极结构的SiC半导体器件的制造工艺的制造工艺中，制造方法有助于在沟槽蚀刻后残留在沟槽内壁上的颗粒和氧化物残余物的去除。

公开(公告)号：US20060256487A1

公开(公告)日：2006-11-16

申请号：US11370188

申请日：2006-03-08

申请人： Daisuke Kishimoto ,  Susumu Iwamoto ,  Katsunori Ueno

发明人： Daisuke Kishimoto ,  Susumu Iwamoto ,  Katsunori Ueno

IPC分类号： H02H7/00

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/157 ,  H01L29/7813 ,  H01L29/7825 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor superjunction device has a superjunction structure formed in a drift region of the device. The superjunction structure has alternately arranged n-type regions and p-type semiconductor regions layered parallel with the drift direction of carriers, permitting current flow when turned ON and depleting when turned OFF. It also includes a first intrinsic semiconductor region between the n-type and p-type regions. The first intrinsic semiconductor region and the n-type and p-type regions sandwiching the first intrinsic semiconductor region forming a unit. A plurality of units are repetitively arranged to form a repetitively arranged structure. The value of mobility of one of electrons in the n-type region or holes in the p-type region is equal to or less than half the value of mobility of corresponding to one of electrons or holes in the first intrinsic semiconductor region. The superjunction structure eliminates the lower limit that prevents further narrowing of the widths of the n-type and p-type regions to further improve the tradeoff relationship between increasing the breakdown voltage and reducing the on-resistance.

摘要翻译： 半导体超结装置具有形成在装置的漂移区域中的超结构结构。 超结构结构交替布置与载流子漂移方向平行分布的n型区域和p型半导体区域，当导通时允许电流流动并且在关断时耗尽。 它还包括n型和p型区之间的第一本征半导体区。 第一本征半导体区域和夹着形成单元的第一本征半导体区域的n型和p型区域。 重复地布置多个单元以形成重复排列的结构。 n型区域中的电子之一或p型区域中的空穴的迁移率的值等于或小于对应于第一本征半导体区域中的电子或空穴之一的迁移率的值的一半。 超结结构消除了阻止n型和p型区域的宽度进一步变窄的下限，以进一步提高增加击穿电压和降低导通电阻之间的折衷关系。