公开(公告)号：US07624498B2

公开(公告)日：2009-12-01

申请号：US11755170

申请日：2007-05-30

申请人： Youn-sung Ko ,  Hak-kyoon Byun ,  Jung-hwan Woo ,  Hyun-jung Song

发明人： Youn-sung Ko ,  Hak-kyoon Byun ,  Jung-hwan Woo ,  Hyun-jung Song

IPC分类号： B23P19/00 ,  H01L21/00

CPC分类号： H01L21/67132 ,  H01L21/67092 ,  Y10T29/41 ,  Y10T29/49815 ,  Y10T29/49819 ,  Y10T29/49824 ,  Y10T29/53091 ,  Y10T29/53187 ,  Y10T29/53274

摘要： An apparatus for and a method of detaching a semiconductor chip from a tape minimize the likelihood that the semiconductor chip will crack. The apparatus includes a holder, a first ejector having an upper end, and a second ejector whose upper end is disposed centrally of that of the first ejector. The holder has an upper portion and a through-hole extending through the upper portion. The ejectors have upper ends that are extendable and retractable out of and back into the holder via the through-hole in the upper portion of the holder. A tape to which at least one semiconductor chip is attached is set against the upper portion of the holder. The first ejector is extended a first distance from the holder to push the semiconductor chip upward. The second ejector is extended from the holder by a second distance larger than the first distance so as to push the semiconductor chip further upward. Thus, the tape is progressively detached from the semiconductor chip.

摘要翻译： 从半导体芯片上分离半导体芯片的方法和方法最小化了半导体芯片会破裂的可能性。 该装置包括保持器，具有上端的第一喷射器和其上端设置在第一喷射器的中心的第二喷射器。 保持器具有延伸穿过上部的上部和通孔。 喷射器具有可以通过保持器上部的通孔而延伸和缩回到保持器内的上端。 安装有至少一个半导体芯片的胶带抵靠着保持器的上部。 第一喷射器从保持器延伸第一距离以向上推半导体芯片。 第二喷射器从保持器延伸大于第一距离的第二距离，以将半导体芯片进一步向上推。 因此，磁带从半导体芯片逐渐分离。

公开(公告)号：US20100037445A1

公开(公告)日：2010-02-18

申请号：US12603913

申请日：2009-10-22

申请人： Youn-sung Ko ,  Hak-kyoon Byun ,  Jung-hwan Woo ,  Hyun-jung Song

发明人： Youn-sung Ko ,  Hak-kyoon Byun ,  Jung-hwan Woo ,  Hyun-jung Song

IPC分类号： B23P19/04

CPC分类号： H01L21/67132 ,  H01L21/67092 ,  Y10T29/49815 ,  Y10T29/49819 ,  Y10T29/49824 ,  Y10T29/53091 ,  Y10T29/53187 ,  Y10T29/53274

摘要： An apparatus for and a method of detaching a semiconductor chip from a tape minimize the likelihood that the semiconductor chip will crack. The apparatus includes a holder, a first ejector having an upper end, and a second ejector whose upper end is disposed centrally of that of the first ejector. The holder has an upper portion and a through-hole extending through the upper portion. The ejectors have upper ends that are extendable and retractable out of and back into the holder via the through-hole in the upper portion of the holder. A tape to which at least one semiconductor chip is attached is set against the upper portion of the holder. The first ejector is extended a first distance from the holder to push the semiconductor chip upward. The second ejector is extended from the holder by a second distance larger than the first distance so as to push the semiconductor chip further upward. Thus, the tape is progressively detached from the semiconductor chip.

摘要翻译： 从半导体芯片上分离半导体芯片的方法和方法最小化了半导体芯片会破裂的可能性。 该装置包括保持器，具有上端的第一喷射器和其上端设置在第一喷射器的中心的第二喷射器。 保持器具有延伸穿过上部的上部和通孔。 喷射器具有可以通过保持器上部的通孔而延伸和缩回到保持器内的上端。 安装有至少一个半导体芯片的胶带抵靠着保持器的上部。 第一喷射器从保持器延伸第一距离以向上推半导体芯片。 第二喷射器从保持器延伸大于第一距离的第二距离，以将半导体芯片进一步向上推。 因此，磁带从半导体芯片逐渐分离。

公开(公告)号：US20070045828A1

公开(公告)日：2007-03-01

申请号：US11509641

申请日：2006-08-25

申请人： Heung-kyu Kwon ,  Se-nyun Kim ,  Tae-hun Kim ,  Jeong-o Ha ,  Hak-kyoon Byun ,  Sung-yong Park

发明人： Heung-kyu Kwon ,  Se-nyun Kim ,  Tae-hun Kim ,  Jeong-o Ha ,  Hak-kyoon Byun ,  Sung-yong Park

IPC分类号： H01L23/34

CPC分类号： H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Disclosed is a semiconductor device packaging technique that is capable of resolving a problem of instability of bonding wires when stacking a plurality of semiconductor chips. The technique is also capable of realizing a slim, light and small package. The semiconductor device package includes a substrate having a substrate pad on a surface thereof, one or more memory chips stacked on the substrate with each memory chip having a pad connected to a common pin receiving a common signal applied to all the memory chips, an interposer chip stacked on the substrate and having an interconnection wire connected to the memory chip pad, the common pin of each of the memory chips being electrically connected to the interconnection wire via the memory chip pad, and a logic chip stacked on the substrate and having a bypass circuit which electrically connects or disconnects the interconnection wire to or from the substrate pad.

摘要翻译： 公开了一种半导体器件封装技术，其能够在堆叠多个半导体芯片时解决接合线不稳定的问题。 该技术还能够实现纤细，轻巧和小包装。 半导体器件封装包括其表面上具有衬底焊盘的衬底，堆叠在衬底上的一个或多个存储器芯片，每个存储器芯片具有连接到接收施加到所有存储器芯片的公共信号的公共引脚的焊盘，插入器 芯片堆叠在基板上并具有连接到存储器芯片焊盘的互连线，每个存储器芯片的公共引脚经由存储器芯片焊盘电连接到互连线，以及堆叠在基板上的逻辑芯片， 旁路电路，其将互连线电连接到基板焊盘或从基板焊盘断开。

公开(公告)号：US07541680B2

公开(公告)日：2009-06-02

申请号：US11509641

申请日：2006-08-25

申请人： Heung-kyu Kwon ,  Se-nyun Kim ,  Tae-hun Kim ,  Jeong-o Ha ,  Hak-kyoon Byun ,  Sung-yong Park

发明人： Heung-kyu Kwon ,  Se-nyun Kim ,  Tae-hun Kim ,  Jeong-o Ha ,  Hak-kyoon Byun ,  Sung-yong Park

IPC分类号： H01L23/12 ,  H01L23/48

CPC分类号： H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Disclosed is a semiconductor device packaging technique that is capable of resolving a problem of instability of bonding wires when stacking a plurality of semiconductor chips. The technique is also capable of realizing a slim, light and small package. The semiconductor device package includes a substrate having a substrate pad on a surface thereof, one or more memory chips stacked on the substrate with each memory chip having a pad connected to a common pin receiving a common signal applied to all the memory chips, an interposer chip stacked on the substrate and having an interconnection wire connected to the memory chip pad, the common pin of each of the memory chips being electrically connected to the interconnection wire via the memory chip pad, and a logic chip stacked on the substrate and having a bypass circuit which electrically connects or disconnects the interconnection wire to or from the substrate pad.

摘要翻译： 公开了一种半导体器件封装技术，其能够在堆叠多个半导体芯片时解决接合线不稳定的问题。 该技术还能够实现纤细，轻巧和小包装。 半导体器件封装包括其表面上具有衬底焊盘的衬底，堆叠在衬底上的一个或多个存储器芯片，每个存储器芯片具有连接到接收施加到所有存储器芯片的公共信号的公共引脚的焊盘，插入器 芯片堆叠在基板上并具有连接到存储器芯片焊盘的互连线，每个存储器芯片的公共引脚经由存储器芯片焊盘电连接到互连线，以及堆叠在基板上的逻辑芯片， 旁路电路，其将互连线电连接到基板焊盘或从基板焊盘断开。

公开(公告)号：US20080111224A1

公开(公告)日：2008-05-15

申请号：US11790962

申请日：2007-04-30

申请人： Hak-kyoon Byun ,  Tae-je Cho ,  Jong-bo Shim ,  Sang-uk Han

发明人： Hak-kyoon Byun ,  Tae-je Cho ,  Jong-bo Shim ,  Sang-uk Han

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L23/3128 ,  H01L23/12 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Embodiments of the present invention provide a MSP having an upper and lower package, with a recess opening in the substrate of the upper package. The upper package may also include multiple stacked semiconductor chips. A lower package may include a substrate and at least one semiconductor chip. During assembly, portions of a lower package are placed into the recess opening in the substrate of the upper package. The beneficial result is a two-package MSP assembly with a reduced total height. In addition, the size and pitch of solder balls or other joints between the upper package substrate and the lower package substrate may also be reduced.

摘要翻译： 本发明的实施例提供了具有上和下封装的MSP，在上封装的基板中具有凹口。 上封装还可以包括多个堆叠的半导体芯片。 下封装可以包括基板和至少一个半导体芯片。 在组装期间，下部包装的部分被放置在上部包装的基底中的凹部开口中。 有利的结果是具有降低的总高度的双封装MSP组件。 此外，也可以减小上封装基板和下封装基板之间的焊球或其他接头的尺寸和间距。