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公开(公告)号：US08698325B2
公开(公告)日：2014-04-15
申请号：US13049915
申请日：2011-03-17
申请人： Wen-Yuan Chang , Yu-Kai Chen , Yeh-Chi Hsu , Ying-Ni Lee , Wei-Chih Lai
发明人： Wen-Yuan Chang , Yu-Kai Chen , Yeh-Chi Hsu , Ying-Ni Lee , Wei-Chih Lai
CPC分类号： H01L24/06 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/02377 , H01L2224/0401 , H01L2224/05008 , H01L2224/05569 , H01L2224/05572 , H01L2224/06155 , H01L2224/16225 , H01L2224/16227 , H01L2924/00 , H01L2924/00013 , H01L2924/00014 , H01L2924/13091 , H01L2924/14 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： An integrated circuit (IC) package includes an IC chip and a package carrier. The IC chip includes a substrate and an IC layered structure configured on an active surface of the substrate. The IC layered structure includes a first physical layer interface and a second physical layer interface. The first physical layer interface includes a plurality of first bump pads and a plurality of first inner pads electrically connected to the first bump pads, respectively. The second physical layer interface includes a plurality of second bump pads and a plurality of second inner pads electrically connected to the second bump pads, respectively. The second bump pads are mirror images of the first bump pads with respect to a first geometric plane perpendicular to the active surface. The second inner pads are mirror images of the first inner pads with respect to the first geometric plane.
摘要翻译： 集成电路（IC）封装包括IC芯片和封装载体。 IC芯片包括基板和构造在基板的有源表面上的IC分层结构。 IC分层结构包括第一物理层接口和第二物理层接口。 第一物理层接口包括分别与第一凸块焊盘电连接的多个第一凸块焊盘和多个第一内焊盘。 第二物理层接口包括分别与第二凸块焊盘电连接的多个第二凸点焊盘和多个第二内焊盘。 第二凸点焊盘是相对于垂直于有源表面的第一几何平面的第一凸点焊盘的镜像。 第二内垫是相对于第一几何平面的第一内垫的镜像。
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公开(公告)号：US20120299192A1
公开(公告)日：2012-11-29
申请号：US13190486
申请日：2011-07-26
申请人： Yu-Kai Chen , Yeh-Chi Hsu
发明人： Yu-Kai Chen , Yeh-Chi Hsu
IPC分类号： H01L23/48
CPC分类号： H01L23/49811 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/05011 , H01L2224/05013 , H01L2224/05015 , H01L2224/05093 , H01L2224/05096 , H01L2224/13006 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2924/00012
摘要： A pad structure is suitable for a circuit carrier or an integrated circuit chip. The pad structure includes an inner pad, a conductive via and an outer pad. The conductive via connects the inner pad. The outer pad connects the conductive via and further connects a conductive ball or a conductive bump. The outer diameter of the outer pad is greater than the outer diameter of the inner pad.
摘要翻译： 垫结构适用于电路载体或集成电路芯片。 垫结构包括内垫，导电孔和外垫。 导电通孔连接内垫。 外垫连接导电通孔，并进一步连接导电球或导电凸块。 外垫的外径大于内垫的外径。
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公开(公告)号：US20120098125A1
公开(公告)日：2012-04-26
申请号：US13049915
申请日：2011-03-17
申请人： Wen-Yuan Chang , Yu-Kai Chen , Yeh-Chi Hsu , Ying-Ni Lee , Wei-Chih Lai
发明人： Wen-Yuan Chang , Yu-Kai Chen , Yeh-Chi Hsu , Ying-Ni Lee , Wei-Chih Lai
IPC分类号： H01L23/50
CPC分类号： H01L24/06 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/02377 , H01L2224/0401 , H01L2224/05008 , H01L2224/05569 , H01L2224/05572 , H01L2224/06155 , H01L2224/16225 , H01L2224/16227 , H01L2924/00 , H01L2924/00013 , H01L2924/00014 , H01L2924/13091 , H01L2924/14 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： An integrated circuit (IC) package includes an IC chip and a package carrier. The IC chip includes a substrate and an IC layered structure configured on an active surface of the substrate. The IC layered structure includes a first physical layer interface and a second physical layer interface. The first physical layer interface includes a plurality of first bump pads and a plurality of first inner pads electrically connected to the first bump pads, respectively. The second physical layer interface includes a plurality of second bump pads and a plurality of second inner pads electrically connected to the second bump pads, respectively. The second bump pads are mirror images of the first bump pads with respect to a first geometric plane perpendicular to the active surface. The second inner pads are mirror images of the first inner pads with respect to the first geometric plane.
摘要翻译： 集成电路（IC）封装包括IC芯片和封装载体。 IC芯片包括基板和构造在基板的有源表面上的IC分层结构。 IC分层结构包括第一物理层接口和第二物理层接口。 第一物理层接口包括分别与第一凸块焊盘电连接的多个第一凸块焊盘和多个第一内焊盘。 第二物理层接口包括分别与第二凸块焊盘电连接的多个第二凸点焊盘和多个第二内焊盘。 第二凸点焊盘是相对于垂直于有源表面的第一几何平面的第一凸点焊盘的镜像。 第二内垫是相对于第一几何平面的第一内垫的镜像。
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公开(公告)号：US08736079B2
公开(公告)日：2014-05-27
申请号：US13190486
申请日：2011-07-26
申请人： Yu-Kai Chen , Yeh-Chi Hsu
发明人： Yu-Kai Chen , Yeh-Chi Hsu
CPC分类号： H01L23/49811 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/05011 , H01L2224/05013 , H01L2224/05015 , H01L2224/05093 , H01L2224/05096 , H01L2224/13006 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2924/00012
摘要： A pad structure is suitable for a circuit carrier or an integrated circuit chip. The pad structure includes an inner pad, a conductive via and an outer pad. The conductive via connects the inner pad. The outer pad connects the conductive via and further connects a conductive ball or a conductive bump. The outer diameter of the outer pad is greater than the outer diameter of the inner pad.
摘要翻译： 垫结构适用于电路载体或集成电路芯片。 垫结构包括内垫，导电孔和外垫。 导电通孔连接内垫。 外垫连接导电通孔，并进一步连接导电球或导电凸块。 外垫的外径大于内垫的外径。
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公开(公告)号：US09418964B2
公开(公告)日：2016-08-16
申请号：US13429441
申请日：2012-03-26
申请人： Wen-Yuan Chang , Yeh-Chi Hsu , Wei-Chih Lai
发明人： Wen-Yuan Chang , Yeh-Chi Hsu , Wei-Chih Lai
IPC分类号： H01L23/48 , H01L25/065 , H01L23/31 , H01L23/00 , H01L25/18
CPC分类号： H01L25/0652 , H01L23/3121 , H01L24/16 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0655 , H01L25/18 , H01L2224/05554 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48111 , H01L2224/48145 , H01L2224/48175 , H01L2224/48227 , H01L2224/4911 , H01L2224/49175 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06558 , H01L2225/06562 , H01L2924/00014 , H01L2924/10162 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A chip package structure includes a carrier and a chip group. The chip group includes a pair of first chips that are identical IC chips. The pair of first chips are disposed on the carrier in opposite directions and parallel to each other, and electrically connected with the carrier.
摘要翻译： 芯片封装结构包括载体和芯片组。 芯片组包括一对相同的IC芯片的第一芯片。 一对第一芯片以相反方向设置在载体上并且彼此平行，并与载体电连接。
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公开(公告)号：US20100155939A1
公开(公告)日：2010-06-24
申请号：US12432367
申请日：2009-04-29
申请人： Wen-Yuan Chang , Wei-Cheng Chen , Yeh-Chi Hsu
发明人： Wen-Yuan Chang , Wei-Cheng Chen , Yeh-Chi Hsu
IPC分类号： H01L23/498 , H05K1/09 , C25D5/02
CPC分类号： H05K3/242 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L24/16 , H01L24/81 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/056 , H01L2224/13099 , H01L2224/16225 , H01L2224/81193 , H01L2224/81801 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H05K3/243 , H05K3/28 , H05K3/4007 , H05K3/4602 , H05K2201/0352 , H05K2201/0367 , H05K2201/09481 , H05K2201/09536 , H05K2201/09627 , H05K2203/054 , H05K2203/0723 , H01L2224/05099
摘要： A fabrication method of a circuit board is provided. A substrate, a top pad, a base pad electrically connecting the top pad, and a top and a base solder resist layers are provided. The top and the base pads are disposed on two opposite surfaces of the substrate, respectively. The top solder resist layer having a first opening partially exposing the top pad and the base solder resist layer having a second opening partially exposing the base pad are disposed on the two surfaces, respectively. A conductive layer covering the base solder resist layer and the base pad is formed. A plating resist layer having a third opening is formed on the conductive layer. A current is applied to the conductive layer through the third opening for electroplating a pre-bump on the top pad. The plating resist layer and the conductive layer are then removed.
摘要翻译： 提供了电路板的制造方法。 提供了一种衬底，顶部焊盘，电连接顶部焊盘以及顶部和基底阻焊层的基座。 顶部和底座分别设置在基板的两个相对的表面上。 具有部分露出顶部焊盘的第一开口和具有部分暴露基板的第二开口的基底阻焊层的顶部阻焊层分别设置在两个表面上。 形成覆盖基底阻焊层和基座的导体层。 在导电层上形成具有第三开口的电镀抗蚀剂层。 通过第三开口将电流施加到导电层，用于在顶部焊盘上电镀预凸块。 然后除去电镀抗蚀剂层和导电层。
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公开(公告)号：US08796848B2
公开(公告)日：2014-08-05
申请号：US13004242
申请日：2011-01-11
申请人： Wen-Yuan Chang , Wei-Cheng Chen , Yeh-Chi Hsu
发明人： Wen-Yuan Chang , Wei-Cheng Chen , Yeh-Chi Hsu
CPC分类号： H05K3/242 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L24/16 , H01L24/81 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/056 , H01L2224/13099 , H01L2224/16225 , H01L2224/81193 , H01L2224/81801 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H05K3/243 , H05K3/28 , H05K3/4007 , H05K3/4602 , H05K2201/0352 , H05K2201/0367 , H05K2201/09481 , H05K2201/09536 , H05K2201/09627 , H05K2203/054 , H05K2203/0723 , H01L2224/05099
摘要： A circuit board includes a substrate that has a top surface and a base surface opposite to each other, at least a top pad disposed on the top surface, a top solder resist layer disposed on the top surface and covering a portion of the top pad, and a pre-bump disposed on the top pad. The top solder resist layer has a first opening exposing a portion of the top pad. The pre-bump is located in the first opening and has a protrusion protruding from the top solder resist layer. A maximum width of the protrusion is less than or equal to a width of the top pad. A chip package structure having the circuit board is also provided.
摘要翻译： 电路板包括具有彼此相对的顶表面和底表面的基底，至少设置在顶表面上的顶垫，设置在顶表面上并覆盖顶垫的一部分的顶部阻焊层， 以及设置在顶垫上的预凸块。 顶部阻焊层具有暴露顶部焊盘的一部分的第一开口。 预凸块位于第一开口中并且具有从顶部阻焊层突出的突起。 突起的最大宽度小于或等于顶垫的宽度。 还提供了具有电路板的芯片封装结构。
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公开(公告)号：US20130175681A1
公开(公告)日：2013-07-11
申请号：US13429441
申请日：2012-03-26
申请人： Wen-Yuan Chang , Yeh-Chi Hsu , Wei-Chih Lai
发明人： Wen-Yuan Chang , Yeh-Chi Hsu , Wei-Chih Lai
IPC分类号： H01L23/498
CPC分类号： H01L25/0652 , H01L23/3121 , H01L24/16 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0655 , H01L25/18 , H01L2224/05554 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48111 , H01L2224/48145 , H01L2224/48175 , H01L2224/48227 , H01L2224/4911 , H01L2224/49175 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06558 , H01L2225/06562 , H01L2924/00014 , H01L2924/10162 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A chip package structure includes a carrier and a chip group. The chip group includes a pair of first chips that are identical IC chips. The pair of first chips are disposed on the carrier in opposite directions and parallel to each other, and electrically connected with the carrier.
摘要翻译： 芯片封装结构包括载体和芯片组。 芯片组包括一对相同的IC芯片的第一芯片。 一对第一芯片以相反方向设置在载体上并且彼此平行，并与载体电连接。
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公开(公告)号：US20110108984A1
公开(公告)日：2011-05-12
申请号：US13004242
申请日：2011-01-11
申请人： Wen-Yuan Chang , Wei-Cheng Chen , Yeh-Chi Hsu
发明人： Wen-Yuan Chang , Wei-Cheng Chen , Yeh-Chi Hsu
IPC分类号： H01L23/498 , H05K1/09
CPC分类号： H05K3/242 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L24/16 , H01L24/81 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/056 , H01L2224/13099 , H01L2224/16225 , H01L2224/81193 , H01L2224/81801 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H05K3/243 , H05K3/28 , H05K3/4007 , H05K3/4602 , H05K2201/0352 , H05K2201/0367 , H05K2201/09481 , H05K2201/09536 , H05K2201/09627 , H05K2203/054 , H05K2203/0723 , H01L2224/05099
摘要： A circuit board includes a substrate that has a top surface and a base surface opposite to each other, at least a top pad disposed on the top surface, a top solder resist layer disposed on the top surface and covering a portion of the top pad, and a pre-bump disposed on the top pad. The top solder resist layer has a first opening exposing a portion of the top pad. The pre-bump is located in the first opening and has a protrusion protruding from the top solder resist layer. A maximum width of the protrusion is less than or equal to a width of the top pad. A chip package structure having the circuit board is also provided.
摘要翻译： 电路板包括具有彼此相对的顶表面和底表面的基底，至少设置在顶表面上的顶垫，设置在顶表面上并覆盖顶垫的一部分的顶部阻焊层， 以及设置在顶垫上的预凸块。 顶部阻焊层具有暴露顶部焊盘的一部分的第一开口。 预凸块位于第一开口中并且具有从顶部阻焊层突出的突起。 突起的最大宽度小于或等于顶垫的宽度。 还提供了具有电路板的芯片封装结构。
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公开(公告)号：US07906377B2
公开(公告)日：2011-03-15
申请号：US12432367
申请日：2009-04-29
申请人： Wen-Yuan Chang , Wei-Cheng Chen , Yeh-Chi Hsu
发明人： Wen-Yuan Chang , Wei-Cheng Chen , Yeh-Chi Hsu
IPC分类号： H01L21/50
CPC分类号： H05K3/242 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L24/16 , H01L24/81 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/056 , H01L2224/13099 , H01L2224/16225 , H01L2224/81193 , H01L2224/81801 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H05K3/243 , H05K3/28 , H05K3/4007 , H05K3/4602 , H05K2201/0352 , H05K2201/0367 , H05K2201/09481 , H05K2201/09536 , H05K2201/09627 , H05K2203/054 , H05K2203/0723 , H01L2224/05099
摘要： A fabrication method of a circuit board is provided. A substrate, a top pad, a base pad electrically connecting the top pad, and a top and a base solder resist layers are provided. The top and the base pads are disposed on two opposite surfaces of the substrate, respectively. The top solder resist layer having a first opening partially exposing the top pad and the base solder resist layer having a second opening partially exposing the base pad are disposed on the two surfaces, respectively. A conductive layer covering the base solder resist layer and the base pad is formed. A plating resist layer having a third opening is formed on the conductive layer. A current is applied to the conductive layer through the third opening for electroplating a pre-bump on the top pad. The plating resist layer and the conductive layer are then removed.
摘要翻译： 提供了电路板的制造方法。 提供了一种衬底，顶部焊盘，电连接顶部焊盘以及顶部和基底阻焊层的基座。 顶部和底座分别设置在基板的两个相对的表面上。 具有部分露出顶部焊盘的第一开口和具有部分暴露基板的第二开口的基底阻焊层的顶部阻焊层分别设置在两个表面上。 形成覆盖基底阻焊层和基座的导体层。 在导电层上形成具有第三开口的电镀抗蚀剂层。 通过第三开口将电流施加到导电层，用于在顶部焊盘上电镀预凸块。 然后除去电镀抗蚀剂层和导电层。
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