公开(公告)号：US06691876B2

公开(公告)日：2004-02-17

申请号：US10056357

申请日：2002-01-25

申请人： Yu-Pin Tsai ,  Chih-Min Pao ,  Ching-Feng Tseng ,  Fu-Tang Chu

发明人： Yu-Pin Tsai ,  Chih-Min Pao ,  Ching-Feng Tseng ,  Fu-Tang Chu

IPC分类号： A47G1908

CPC分类号： H01L21/6732 ,  H01L21/67326

摘要： A semiconductor wafer cassette has a first side wall, a second side wall opposite the first side wall, a front surface, and a back surface opposite the front surface. A body defines an internal bay portion with slots for vertically receiving wafers, each slot of the internal bay portion having one support slab. The body also includes two parallel legs for supporting the cassette and a handle for handling the cassette.

摘要翻译： 半导体晶片盒具有第一侧壁，与第一侧壁相对的第二侧壁，前表面和与前表面相对的后表面。 主体限定具有用于垂直接收晶片的槽的内部间隔部分，内部间隔部分的每个槽具有一个支撑板。 该主体还包括用于支撑盒的两个平行腿和用于处理盒的手柄。

公开(公告)号：US20070155049A1

公开(公告)日：2007-07-05

申请号：US11559036

申请日：2006-11-13

申请人： Yu-Pin Tsai

发明人： Yu-Pin Tsai

IPC分类号： H01L21/00

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/12105 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2224/05099

摘要： A wafer-level method for manufacturing a chip package structure is disclosed. A wafer comprises a first surface and a second surface opposite thereto. The first surface has chip units disposed thereon to define scribe lines. An adhesive material is disposed between the first surface and the transparent glass for adhering the wafer to a transparent glass and leaving no gap between the first surface and the transparent glass. The wafer is vertically cut from the second surface corresponding to each scribe line of the first surface to the encapsulation adhesive material for forming scribe grooves, and then the second surface is coated with an encapsulation material for filling the scribe grooves. After removing the adhesive material and the transparent glass, the encapsulation material in each of the scribe grooves is vertically cut from the first surface, so as to form chip package structures.

摘要翻译： 公开了用于制造芯片封装结构的晶片级方法。 晶片包括第一表面和与其相对的第二表面。 第一表面具有设置在其上的芯片单元以限定划线。 粘合材料设置在第一表面和透明玻璃之间，用于将晶片粘附到透明玻璃上，并且在第一表面和透明玻璃之间不留下间隙。 将晶片从对应于第一表面的每个划线的第二表面垂直切割到用于形成划线槽的封装粘合剂材料，然后第二表面涂覆有用于填充划线槽的封装材料。 在去除粘合剂材料和透明玻璃之后，每个划线槽中的封装材料从第一表面垂直切割，以形成芯片封装结构。

公开(公告)号：US07842597B2

公开(公告)日：2010-11-30

申请号：US11162898

申请日：2005-09-27

申请人： Yu-Pin Tsai

发明人： Yu-Pin Tsai

IPC分类号： H01L21/44

CPC分类号： H01L24/97 ,  H01L23/3128 ,  H01L23/3677 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package includes a semiconductor substrate, conductive plugs and a chip. Wherein, the conductive plugs perforate the semiconductor substrate. Besides, the chip is disposed on a surface of the semiconductor substrate and electrically connected to the conductive plugs. Based on the above-described design, the chip package is capable of reducing the thermal stress problem caused by a coefficient of thermal expansion (CTE) dismatch compared with the prior art. The present invention discloses further a chip packaging process and furthermore a chip carrier and the process thereof.

摘要翻译： 芯片封装包括半导体衬底，导电插头和芯片。 其中，导电插塞穿透半导体衬底。 此外，芯片设置在半导体衬底的表面上并与导电插头电连接。 基于上述设计，与现有技术相比，芯片封装能够减少由热膨胀系数（CTE）引起的热应力问题。 本发明进一步公开了一种芯片封装方法以及芯片载体及其工艺。

公开(公告)号：US20060256222A1

公开(公告)日：2006-11-16

申请号：US11164891

申请日：2005-12-09

申请人： Yu-Pin Tsai

发明人： Yu-Pin Tsai

IPC分类号： H04N5/335

CPC分类号： H04N5/2253 ,  H01L27/14618 ,  H01L27/14685 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

摘要： A method of fabricating a CMOS image sensor (CIS) package includes: providing a transparent substrate, in which the transparent substrate includes a cavity; disposing an image sensor chip in the cavity and forming a plurality of bumps between the image sensor chip and the transparent substrate, in which the image sensor chip includes a light sensitive area; forming a barrier wall between the transparent substrate and the image sensor chip, in which the barrier wall further forms a circular pattern around the light sensitive area of the image sensor chip; and forming an underfill layer between the transparent substrate and the image sensor chip for forming a package structure.

摘要翻译： 制造CMOS图像传感器（CIS）封装的方法包括：提供透明基板，其中所述透明基板包括空腔; 将图像传感器芯片设置在空腔中，并在图像传感器芯片和透明基板之间形成多个凸起，其中图像传感器芯片包括光敏区域; 在透明基板和图像传感器芯片之间形成阻挡壁，其中阻挡壁进一步在图像传感器芯片的感光区域周围形成圆形图案; 以及在所述透明基板和用于形成封装结构的图像传感器芯片之间形成底层填充层。

公开(公告)号：US08728915B2

公开(公告)日：2014-05-20

申请号：US13225756

申请日：2011-09-06

申请人： Yu-Pin Tsai ,  Cheng-I Huang ,  Yao-Hui Hu

发明人： Yu-Pin Tsai ,  Cheng-I Huang ,  Yao-Hui Hu

IPC分类号： H01L21/268 ,  H01L29/06 ,  H01L21/683 ,  H01L23/544 ,  H01L23/00

CPC分类号： H01L21/6836 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2223/54433 ,  H01L2224/16 ,  H01L2924/01025 ,  H01L2924/01084 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/00

摘要： A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is thinned. Then, the thinned wafer is fixed on a non-UV tape such that the second surface of the wafer is attached to the tape. Finally, the laser marking step is performed, such that a laser light penetrates the non-UV tape and marks a pattern on the second surface of the wafer. According to the laser-marking method of the embodiment, the pattern is formed by the non-UV residuals left on the second surface of the wafer, and the components of the glue residuals at least include elements of silicon and carbon.

摘要翻译： 提供了晶片激光打标方法。 首先，提供具有彼此相对的第一表面（活性表面）和第二表面（背面）的晶片。 接下来，晶片变薄。 然后，将薄的晶片固定在非UV带上，使得晶片的第二表面附接到带上。 最后，执行激光标记步骤，使得激光穿透非UV带并且在晶片的第二表面上标记图案。 根据本实施例的激光标记方法，图案由残留在晶片的第二表面上的非UV残余物形成，并且胶合残余物的成分至少包括硅和碳的元素。

公开(公告)号：US20110241194A1

公开(公告)日：2011-10-06

申请号：US12753843

申请日：2010-04-02

申请人： Chia-Ching Chen ,  Yu-Pin Tsai

发明人： Chia-Ching Chen ,  Yu-Pin Tsai

IPC分类号： H01L25/065 ,  H01L23/538

CPC分类号： H01L25/03 ,  H01L24/19 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An embodiment of a stacked package assembly includes: (1) a first semiconductor device package including: (a) a semiconductor device including back and lateral surfaces; (b) a package body including an upper surface and substantially covering the back and lateral surfaces of the device; and (c) a first conductive contact adjacent to the upper surface of the body and electrically connected to the device; (2) a second semiconductor device package disposed above the upper surface of the body; (3) a conductive bump adjacent to the first contact and to the second device package; (4) a second conductive contact external to the first and the second device packages; and (5) a conductive wire electrically connecting the first and the second device packages to the second contact, a first end of the wire adjacent to the first contact and at least partially covered by the bump.

摘要翻译： 堆叠封装组件的实施例包括：（1）第一半导体器件封装，包括：（a）包括背面和侧表面的半导体器件; （b）包装体，其包括上表面并且基本上覆盖所述装置的后表面和侧表面; 和（c）邻近所述主体的上表面并电连接到所述装置的第一导电接触件; （2）设置在所述主体的上表面上方的第二半导体器件封装; （3）邻近所述第一触点和所述第二器件封装的导电凸块; （4）在第一和第二器件封装外部的第二导电触点; 以及（5）将所述第一和第二器件封装电连接到所述第二触点的导线，所述导线的与所述第一触点相邻并且至少部分地被所述凸块覆盖的第一端。

公开(公告)号：US20060057778A1

公开(公告)日：2006-03-16

申请号：US11162606

申请日：2005-09-16

申请人： Yu-Pin Tsai

发明人： Yu-Pin Tsai

IPC分类号： H01L21/78

CPC分类号： H01L21/56 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/544 ,  H01L24/27 ,  H01L2221/6834 ,  H01L2223/5448 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/73104 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05599

摘要： A fabricating method of wafer protection layers and a wafer structure are provided. The fabricating method includes providing a wafer first. The wafer includes pluralities of chips and has an active surface, a corresponding reverse surface and a plurality of pre-cut trenches on the active surface. On the active surface, pluralities of bumps are disposed. Next, a first curing-type protection layer and a pellicle are disposed over the active surface. Afterwards, the first curing-type protection layer is asked to contact the active surface. Besides, a second curing-type protection layer is disposed on the reverse surface. Afterward, the first and the second curing-type protection layer are cured. Finally, the wafer is cut through the pre-cut trenches to separate the chips from the wafer.

摘要翻译： 提供了晶片保护层和晶片结构的制造方法。 制造方法包括首先提供晶片。 晶片包括多个芯片，并且在活性表面上具有活性表面，相应的反面和多个预切割沟槽。 在活性表面上设置有多个凸块。 接下来，在活性表面上设置第一固化型保护层和防护薄膜。 之后，要求第一固化型保护层与活性表面接触。 此外，第二固化型保护层设置在反面上。 之后，固化第一固化型保护层和第二固化型保护层。 最后，通过预切割沟槽切割晶片以将芯片与晶片分离。

公开(公告)号：US20100001416A1

公开(公告)日：2010-01-07

申请号：US12482131

申请日：2009-06-10

申请人： Yu-Pin Tsai ,  Cheng-Yi Huang ,  Yao-Hui Hu

发明人： Yu-Pin Tsai ,  Cheng-Yi Huang ,  Yao-Hui Hu

IPC分类号： H01L23/544 ,  H01L21/304

CPC分类号： H01L23/544 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/0401

摘要： A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is thinned. Then, the thinned wafer is fixed on a tape such that the second surface of the wafer is attached to the tape. Finally, the laser marking step is performed, such that a laser light penetrates the tape and marks a pattern on the second surface of the wafer. There are glue residuals remained in the laser-marking pattern of the die manufactured according to the laser-marking method of the invention, and the components of the glue residuals at least include elements of silicon, carbon and oxygen.

摘要翻译： 提供了晶片激光打标方法。 首先，提供具有彼此相对的第一表面（活性表面）和第二表面（背面）的晶片。 接下来，晶片变薄。 然后，将薄的晶片固定在带上，使得晶片的第二表面附接到带上。 最后，执行激光标记步骤，使得激光穿透带并在晶片的第二表面上标记图案。 根据本发明的激光标记方法制造的模具的激光标记图案中残留有胶合残留物，并且胶残留物的成分至少包括硅，碳和氧的元素。

公开(公告)号：US07510909B2

公开(公告)日：2009-03-31

申请号：US11162606

申请日：2005-09-16

申请人： Yu-Pin Tsai

发明人： Yu-Pin Tsai

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/56 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/544 ,  H01L24/27 ,  H01L2221/6834 ,  H01L2223/5448 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/73104 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05599

摘要： A fabricating method of wafer protection layers and a wafer structure are provided. The fabricating method includes providing a wafer first. The wafer includes pluralities of chips and has an active surface, a corresponding reverse surface and a plurality of pre-cut trenches on the active surface. On the active surface, pluralities of bumps are disposed. Next, a first curing-type protection layer and a pellicle are disposed over the active surface. Afterwards, the first curing-type protection layer is asked to contact the active surface. Besides, a second curing-type protection layer is disposed on the reverse surface. Afterward, the first and the second curing-type protection layer are cured. Finally, the wafer is cut through the pre-cut trenches to separate the chips from the wafer.

摘要翻译： 提供了晶片保护层和晶片结构的制造方法。 该制造方法包括首先提供晶片。 晶片包括多个芯片，并且在活性表面上具有活性表面，相应的反面和多个预切割沟槽。 在活性表面上设置有多个凸块。 接下来，在活性表面上设置第一固化型保护层和防护薄膜。 之后，要求第一固化型保护层与活性表面接触。 此外，第二固化型保护层设置在反面上。 之后，固化第一固化型保护层和第二固化型保护层。 最后，通过预切割沟槽切割晶片以将芯片与晶片分离。

公开(公告)号：US07560818B2

公开(公告)日：2009-07-14

申请号：US11878456

申请日：2007-07-24

申请人： Yu-Pin Tsai

发明人： Yu-Pin Tsai

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L24/94 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04073 ,  H01L2224/05553 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/49171 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/078 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2924/351 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2224/48227 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/32225 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked structure of chips including a first chip, a second chip, an insulation layer and a first conductive element is provided. The second chip is attached to the first chip, and the back surface of the second chip faces an active surface of the first chip. The second chip includes a first contact disposed on an active surface of the second chip. The insulation layer disposed on the active surface of the first chip encapsulates the second chip. The first conductive element is formed in the insulation layer for electrically connecting one end of the first conductive element to the first contact and the other end of the first conductive element exposed outside the insulation layer. A wafer structure for making the stacked structure of chips is also provided. The stacked structure of chips has no circuit carrier, hence reducing the thickness of the stacked structure.

摘要翻译： 提供了包括第一芯片，第二芯片，绝缘层和第一导电元件的芯片的堆叠结构。 第二芯片附接到第一芯片，并且第二芯片的背表面面向第一芯片的有效表面。 第二芯片包括设置在第二芯片的有源表面上的第一触点。 设置在第一芯片的有源表面上的绝缘层封装第二芯片。 第一导电元件形成在绝缘层中，用于将第一导电元件的一端电连接到第一触点，暴露在绝缘层外部的第一导电元件的另一端。 还提供了用于制造芯片堆叠结构的晶片结构。 芯片的堆叠结构没有电路载体，因此减小了堆叠结构的厚度。