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    Circuit and method for generating circuit power on reset signal
    1.
    发明申请
    Circuit and method for generating circuit power on reset signal 有权
    用于产生电路上电复位信号的电路和方法

    公开(公告)号：US20070170961A1

    公开(公告)日：2007-07-26

    申请号：US11366694

    申请日：2006-03-02

    申请人： Chun-Yao Liao ,  Yu-Ren Chen

    发明人： Chun-Yao Liao ,  Yu-Ren Chen

    IPC分类号： H03L7/00

    CPC分类号： H03K17/223 ,  G06F1/24 ,  H03K17/161 ,  H03K17/284

    摘要： Disclosed is an improved circuit and method for generating a power on reset signal, the circuit being a two-stage circuit comprising a delay-stage circuit and an output-stage circuit. The delay-stage circuit delays a time for a power on reset signal generated in the output-stage circuit changing from low to high, so that a power voltage having a low rising speed may be normally reset. Further, the two stages provide charging paths and discharging paths so that the power on reset signal may be prevented from changing from high to low when it has changed from low to high, when noises are presented on the power voltage.

    摘要翻译： 公开了一种用于产生上电复位信号的改进的电路和方法，该电路是包括延迟级电路和输出级电路的两级电路。 延迟级电路延迟在输出级电路中产生的上电复位信号从低变为高的时间，使得具有低上升速度的电源电压可以被正常复位。 此外，两级提供充电路径和放电路径，使得当在电源电压上呈现噪声时，当从低电平变为高电平时，可以防止上电复位信号从高电平变为低电平。

    Fuse option circuit
    2.
    发明授权
    Fuse option circuit 有权
    保险丝选项电路

    公开(公告)号：US07663425B2

    公开(公告)日：2010-02-16

    申请号：US12313874

    申请日：2008-11-24

    申请人： Yu-Ren Chen ,  Chun-Yao Liao

    发明人： Yu-Ren Chen ,  Chun-Yao Liao

    IPC分类号： H01H37/76

    CPC分类号： G11C17/16 ,  G11C17/18 ,  G11C29/789

    摘要： A fuse option circuit including a fuse, a control switch, a latch, and a logical operational controller is provided. The latch stores a selected level. The logical operational controller outputs a selected result signal and feedbacks a control signal to the control switch. The level of the control signal determines whether the control switch is on or off. Therefore, the required level is input to the latch and the working mode having an ultra low current is selected. Furthermore, when the fuse is in an untrimmed state, the level of the selected result signal could be selected by a reset pulse signal of the latch in order to test a product. Afterward, it is determined whether the fuse is trimmed or not. When the fuse is in a trimmed state, the level of the selected result signal is established by a rising edge of the reset pulse signal.

    摘要翻译： 提供了包括保险丝，控制开关，锁存器和逻辑运算控制器的保险丝选择电路。 锁存器存储所选的电平。 逻辑运算控制器输出选定的结果信号并将控制信号反馈给控制开关。 控制信号的电平决定控制开关是开或关。 因此，所需的电平被输入到锁存器，并且选择具有超低电流的工作模式。 此外，当保险丝处于未修复状态时，可以通过锁存器的复位脉冲信号来选择所选择的结果信号的电平，以便测试产品。 之后，确定保险丝是否被修剪。 当保险丝处于调整状态时，所选择的结果信号的电平由复位脉冲信号的上升沿建立。

    Fuse option circuit
    3.
    发明申请
    Fuse option circuit 有权

    公开(公告)号：US20090128226A1

    公开(公告)日：2009-05-21

    申请号：US12313874

    申请日：2008-11-24

    申请人： Yu-Ren Chen ,  Chun-Yao Liao

    发明人： Yu-Ren Chen ,  Chun-Yao Liao

    IPC分类号： G11C17/16

    CPC分类号： G11C17/16 ,  G11C17/18 ,  G11C29/789

    摘要： A fuse option circuit including a fuse, a control switch, a latch, and a logical operational controller is provided. The latch stores a selected level. The logical operational controller outputs a selected result signal and feedbacks a control signal to the control switch. The level of the control signal determines whether the control switch is on or off. Therefore, the required level is input to the latch and the working mode having an ultra low current is selected. Furthermore, when the fuse is in an untrimmed state, the level of the selected result signal could be selected by a reset pulse signal of the latch in order to test a product. Afterward, it is determined whether the fuse is trimmed or not. When the fuse is in a trimmed state, the level of the selected result signal is established by a rising edge of the reset pulse signal.

    Fuse option circuit
    4.
    发明授权
    Fuse option circuit 有权
    保险丝选项电路

    公开(公告)号：US07532058B2

    公开(公告)日：2009-05-12

    申请号：US11888137

    申请日：2007-07-30

    申请人： Yu-Ren Chen ,  Chun-Yao Liao

    发明人： Yu-Ren Chen ,  Chun-Yao Liao

    IPC分类号： H01H37/76

    CPC分类号： G11C17/16 ,  G11C17/18 ,  G11C29/789

    摘要： A fuse option circuit including a fuse, a control switch, a latch, and a logical operational controller is provided. The latch stores a selected level. The logical operational controller outputs a selected result signal and feedbacks a control signal to the control switch. The level of the control signal determines whether the control switch is on or off. Therefore, the required level is input to the latch and the working mode having an ultra low current is selected. Furthermore, when the fuse is in an untrimmed state, the level of the selected result signal could be selected by a reset pulse signal of the latch in order to test a product. Afterward, it is determined whether the fuse is trimmed or not. When the fuse is in a trimmed state, the level of the selected result signal is established by a rising edge of the reset pulse signal.

    摘要翻译： 提供了包括保险丝，控制开关，锁存器和逻辑运算控制器的保险丝选择电路。 锁存器存储所选的电平。 逻辑运算控制器输出选定的结果信号并将控制信号反馈给控制开关。 控制信号的电平决定控制开关是开或关。 因此，所需的电平被输入到锁存器，并且选择具有超低电流的工作模式。 此外，当保险丝处于未修复状态时，可以通过锁存器的复位脉冲信号来选择所选择的结果信号的电平，以便测试产品。 之后，确定保险丝是否被修剪。 当保险丝处于调整状态时，所选择的结果信号的电平由复位脉冲信号的上升沿建立。

    Fuse option circuit
    5.
    发明申请
    Fuse option circuit 有权
    保险丝选项电路

    公开(公告)号：US20080061866A1

    公开(公告)日：2008-03-13

    申请号：US11888137

    申请日：2007-07-30

    申请人： Yu-Ren Chen ,  Chun-Yao Liao

    发明人： Yu-Ren Chen ,  Chun-Yao Liao

    IPC分类号： G11C17/16

    CPC分类号： G11C17/16 ,  G11C17/18 ,  G11C29/789

    摘要： A fuse option circuit including a fuse, a control switch, a latch, and a logical operational controller is provided. The latch stores a selected level. The logical operational controller outputs a selected result signal and feedbacks a control signal to the control switch. The level of the control signal determines whether the control switch is on or off. Therefore, the required level is input to the latch and the working mode having an ultra low current is selected. Furthermore, when the fuse is in an untrimmed state, the level of the selected result signal could be selected by a reset pulse signal of the latch in order to test a product. Afterward, it is determined whether the fuse is trimmed or not. When the fuse is in a trimmed state, the level of the selected result signal is established by a rising edge of the reset pulse signal.

    摘要翻译： 提供了包括保险丝，控制开关，锁存器和逻辑运算控制器的保险丝选择电路。 锁存器存储所选的电平。 逻辑运算控制器输出选定的结果信号并将控制信号反馈给控制开关。 控制信号的电平决定控制开关是开或关。 因此，所需的电平被输入到锁存器，并且选择具有超低电流的工作模式。 此外，当保险丝处于未修复状态时，可以通过锁存器的复位脉冲信号来选择所选择的结果信号的电平，以便测试产品。 之后，确定保险丝是否被修剪。 当保险丝处于调整状态时，所选择的结果信号的电平由复位脉冲信号的上升沿建立。

    Chip package
    6.
    发明授权
    Chip package 有权
    芯片封装

    公开(公告)号：US07932531B2

    公开(公告)日：2011-04-26

    申请号：US12506255

    申请日：2009-07-21

    申请人： Chun-Ying Lin ,  Ya-Chi Chen ,  Yu-Ren Chen ,  I-Hsin Mao

    发明人： Chun-Ying Lin ,  Ya-Chi Chen ,  Yu-Ren Chen ,  I-Hsin Mao

    IPC分类号： H01L33/00

    CPC分类号： H01L21/563 ,  H01L23/3135 ,  H01L24/97 ,  H01L33/642 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

    摘要： A chip package includes a thermal enhanced plate, contacts around the thermal enhanced plate and electrically insulated from the thermal enhanced plate, a film-like circuit layer disposed on the contacts and the thermal enhanced plate, a conductive adhesive layer, a first molding, and at least one chip disposed on the film-like circuit layer. The conductive adhesive layer is disposed between the contacts and the film-like circuit layer electrically connected to the contacts through the conductive adhesive layer. The chip has a back surface, an active surface and many bumps disposed thereon, and the chip is electrically connected to the film-like circuit layer via the bumps. The first molding at least encapsulates a portion of the thermal enhanced plate, the conductive adhesive layer, parts of the contacts and at least a portion of the film-like circuit layer. Therefore, heat dissipation efficiency of the light emitting chip package is improved.

    摘要翻译： 芯片封装包括热增强板，围绕热增强板接触并与热增强板电绝缘，设置在触点和热增强板上的膜状电路层，导电粘合剂层，第一模制件和 设置在膜状电路层上的至少一个芯片。 导电性粘合剂层设置在触点和通过导电粘合剂层与触点电连接的膜状电路层之间。 芯片具有背面，有源表面和设置在其上的许多凸块，并且芯片经由凸块电连接到膜状电路层。 第一模制品至少封装热增强板的一部分，导电粘合剂层，触点的一部分和膜状电路层的至少一部分。 因此，提高了发光芯片封装的散热效率。

    Multi-Chip Stacked Package Structure
    7.
    发明申请
    Multi-Chip Stacked Package Structure 审中-公开
    多芯片堆叠封装结构

    公开(公告)号：US20090072361A1

    公开(公告)日：2009-03-19

    申请号：US12122779

    申请日：2008-05-19

    申请人： Geng-Shin SHEN ,  Yu-Ren Chen

    发明人： Geng-Shin SHEN ,  Yu-Ren Chen

    IPC分类号： H01L23/495

    CPC分类号： H01L23/4951 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012

    摘要： A multi-chip stacked package structure, comprising: a lead-frame having a top surface a back surface, the inner leads comprising a plurality of first inner leads and a plurality of second inner leads in parallel; a first chip fixedly connected to the back surface of the lead-frame, and the first chip having an active surface and a plurality of first pads adjacent to the central area of the active surface; a plurality of first metal wires electrically connected the first inner leads and the second inner leads and the first pads on the active surface of the first chip; a second chip fixedly connected to the top surface of the lead-frame, and the second chip having an active surface and a plurality of second pads adjacent to the central area of the active surface; a pair of the spacers provided on the thermal fin of the lead-frame; a plurality of second metal wires electrically connected to the top surface of first inner leads and the second inner leads and the second pads on the active surface of the second chip; and a package body encapsulated the first chip, the plurality of metal wires the second chip, the plurality of pads, the first inner leads and the second inner leads and to expose the outer leads.

    摘要翻译： 一种多芯片堆叠封装结构，包括：具有顶表面的后表面的引线框架，所述内引线包括多个第一内引线和多个第二内引线并联; 第一芯片固定地连接到引线框架的背面，并且第一芯片具有活性表面和与活性表面的中心区域相邻的多个第一焊盘; 多个第一金属线，电连接第一内引线和第二内引线以及第一芯片的有效表面上的第一焊盘; 固定地连接到引线框架的顶表面的第二芯片，并且第二芯片具有活动表面和与活动表面的中心区域相邻的多个第二焊盘; 设置在引线框架的散热片上的一对间隔件; 多个第二金属线，电连接到第一内引线的顶表面，第二内引线和第二芯片的有效表面上的第二焊盘; 以及封装体，其包封所述第一芯片，所述多个金属线，所述第二芯片，所述多个焊盘，所述第一内引线和所述第二内引线，以及露出所述外引线。

    Method for Fabricating Multi-Chip Stacked Package
    10.
    发明申请
    Method for Fabricating Multi-Chip Stacked Package 有权
    多芯片堆叠封装方法

    公开(公告)号：US20090075426A1

    公开(公告)日：2009-03-19

    申请号：US12134336

    申请日：2008-06-06

    申请人： Geng-Shin SHEN ,  Yu-Ren Chen

    发明人： Geng-Shin SHEN ,  Yu-Ren Chen

    IPC分类号： H01L21/02

    CPC分类号： H01L23/49575 ,  H01L23/4951 ,  H01L23/49513 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

    摘要： A multi-chips stacked package method which includes providing a lead frame includes a top surface and a reverse surface formed by a plurality of inner leads and a plurality of outer leads; fixing a first chip on the reverse surface of the lead frame and the active surface of the first chip includes a plurality of first pads closed to the central region; forming a plurality of first metal wires, and the first pads are electrically connected to the first inner leads and the second inner leads by the first metal wires; forming a plurality of metal spacers on the thermal fin of the lead frame; fixing a second chip to electrically connect to the top surface of the first inner leads and the second inner leads; forming a plurality of second metal wires, and the second pads are electrically connected to the top surface of the first inner leads and the second inner leads; and flowing a molding to form an encapsulated material to cover the first chip, the first metal wires, the second chip, the second metal wires, the first inner leads and the second inner leads and the outer leads being exposed.

    摘要翻译： 包括提供引线框架的多芯片堆叠封装方法包括由多个内引线和多个外引线形成的顶表面和反面; 将第一芯片固定在引线框架的相反表面上，并且第一芯片的有效表面包括多个靠近中心区域的第一焊盘; 形成多个第一金属线，并且所述第一焊盘通过所述第一金属线电连接到所述第一内引线和所述第二内引线; 在引线框架的散热片上形成多个金属间隔物; 固定第二芯片以电连接到第一内引线和第二内引线的顶表面; 形成多个第二金属线，并且所述第二焊盘电连接到所述第一内引线和所述第二内引线的顶表面; 并且使模制件流动以形成覆盖第一芯片的封装材料，第一金属线，第二芯片，第二金属线，第一内引线和第二内引线以及外引线露出。