公开(公告)号：US20090140322A1

公开(公告)日：2009-06-04

申请号：US11992961

申请日：2006-10-03

申请人： Takashi Nakagawa ,  Yukishige Saito

发明人： Takashi Nakagawa ,  Yukishige Saito

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/42332 ,  H01L29/40114 ,  H01L29/7881

摘要： A first insulation film (silicon dioxide film) and a second insulation film (aluminum oxide film) are laminated on a surface of a silicon substrate in this order to form a gate insulation film. At least one element (aluminum) of elements, which constitutes the second insulation film but is different from elements commonly contained in the whole area of the first insulation film, is caused to be contained in a part of the first insulation film, whereby a charge trapping site region is formed in the first insulation film.

摘要翻译： 依次将第一绝缘膜（二氧化硅膜）和第二绝缘膜（氧化铝膜）层叠在硅基板的表面上，形成栅绝缘膜。 构成第二绝缘膜但与第一绝缘膜的整个区域中通常包含的元件不同的元件的至少一个元件（铝）被包含在第一绝缘膜的一部分中，由此， 捕获位置区域形成在第一绝缘膜中。

公开(公告)号：US07211517B2

公开(公告)日：2007-05-01

申请号：US10476978

申请日：2002-09-05

申请人： Yukishige Saito ,  Risho Koh ,  Jyonu Ri ,  Hisashi Takemura

发明人： Yukishige Saito ,  Risho Koh ,  Jyonu Ri ,  Hisashi Takemura

IPC分类号： H01L21/311

CPC分类号： H01L29/66757 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78636 ,  Y10S438/978

摘要： A method of manufacturing a semiconductor device of the present invention includes (a) sequentially forming a gate insulating film 14, a first conductive layer 15 and a first insulating film 16 on a semiconductor layer 13 provided on an insulating film 12; (b) selectively removing the semiconductor layer, the gate insulating film, the first conductive layer and the first insulating film to form a device isolation trench; (c) forming a second insulating film 17 in the device isolation [element separation] trench, wherein a height of an upper surface of the second insulating film is substantially coincident with that of an upper surface of the first insulating film; (d) removing a part of the second insulating film and the first insulating film such that a height of an upper surface of the exposed first conductive layer is substantially coincident with that of the top surface of the second insulating film; and (e) patterning the first conductive layer to form a gate electrode.

摘要翻译： 本发明的半导体器件的制造方法包括：（a）在设置在绝缘膜12上的半导体层13上依次形成栅极绝缘膜14，第一导电层15和第一绝缘膜16; （b）选择性地去除半导体层，栅极绝缘膜，第一导电层和第一绝缘膜，以形成器件隔离沟槽; （c）在器件隔离[元件分离]沟槽中形成第二绝缘膜17，其中第二绝缘膜的上表面的高度与第一绝缘膜的上表面的高度基本一致; （d）去除第二绝缘膜和第一绝缘膜的一部分，使得暴露的第一导电层的上表面的高度与第二绝缘膜的顶表面的高度基本一致; 和（e）图案化第一导电层以形成栅电极。

公开(公告)号：US07611934B2

公开(公告)日：2009-11-03

申请号：US11182150

申请日：2005-07-15

申请人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

发明人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

公开(公告)号：US06975001B2

公开(公告)日：2005-12-13

申请号：US10163984

申请日：2002-06-06

申请人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

发明人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

摘要翻译： 半导体器件包括（a）形成在电绝缘层上的半导体层，（b）形成在半导体层上的栅极绝缘膜，（c）形成在栅极绝缘膜上的栅电极，以及（d）场绝缘 在半导体层上形成用于限定要制造半导体器件的区域的膜。 半导体层包括（a1）形成在栅极周围的半导体层中的源极和漏极区，源极和漏极区包含第一导电型杂质，（a2）形成在半导体层中的体接触区域， 包含第二导电型杂质，以及（a3）形成在半导体层中的载流子路径区域，使得载流子路径区域不与源区域和漏极区域接触，但与体接触区域接触，载体路径区域 含有第二导电型杂质。

公开(公告)号：US09059402B2

公开(公告)日：2015-06-16

申请号：US13380092

申请日：2010-06-21

申请人： Munehiro Tada ,  Toshitsugu Sakamoto ,  Yuko Yabe ,  Yukishige Saito ,  Hiromitsu Hada

发明人： Munehiro Tada ,  Toshitsugu Sakamoto ,  Yuko Yabe ,  Yukishige Saito ,  Hiromitsu Hada

IPC分类号： H01L45/00 ,  G11C13/00

CPC分类号： H01L45/1233 ,  G11C13/0011 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/56 ,  H01L45/085 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625

摘要： A resistance-variable element as disclosed has high reliability, high densification, and good insulating properties. The device provides a resistance-variable element in which a first electrode including a metal primarily containing copper, an oxide film of valve-metal, an ion-conductive layer containing oxygen and a second electrode are laminated in this order.

摘要翻译： 所公开的电阻可变元件具有高可靠性，高密度化和良好的绝缘性能。 该装置提供一种电阻可变元件，其中包括主要包含铜的金属，阀金属的氧化物膜，含氧的离子传导层和第二电极的第一电极按此顺序层压。

公开(公告)号：US06916695B2

公开(公告)日：2005-07-12

申请号：US10188642

申请日：2002-07-03

申请人： Hitoshi Wakabayashi ,  Yukishige Saito

发明人： Hitoshi Wakabayashi ,  Yukishige Saito

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/76 ,  H01L29/78 ,  H01L31/119

CPC分类号： H01L29/66606 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S257/915

摘要： One object of the present invention is to suppress a threshold voltage of at least an n-channel MISFET using a nitride of a high melting point metal at it's gate electrode. In order to achieve the object, a gate electrode 109 of a p-channel MISFET is constituted of a titanium nitride film 106 and a tungsten film 107 formed on the film 106 and a gate electrode 110a of an n-channel MISFET is constituted of a titanium nitride film 106a and a tungsten film 107 formed on the film 106a. The titanium nitride film 106a is formed by nitrogen ion implantation in the titanium nitride film 106 to decrease the work function.

摘要翻译： 本发明的一个目的是在其栅极处抑制使用高熔点金属的氮化物的至少n沟道MISFET的阈值电压。 为了实现该目的，p沟道MISFET的栅电极109由形成在膜106上的氮化钛膜106和钨膜107构成，并且n沟道MISFET的栅极110a由 形成在膜106a上的氮化钛膜106a和钨膜107。 通过氮化钛膜106中的氮离子注入形成氮化钛膜106a以降低功函数。

公开(公告)号：US08946668B2

公开(公告)日：2015-02-03

申请号：US13574405

申请日：2011-01-21

申请人： Yukishige Saito ,  Kimihiko Ito ,  Hiromitsu Hada

发明人： Yukishige Saito ,  Kimihiko Ito ,  Hiromitsu Hada

IPC分类号： H01L29/02 ,  H01L47/00 ,  H01L23/522 ,  H01L45/00

CPC分类号： H01L23/5228 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a semiconductor device including a resistive change element between a first wiring and a second wiring, which are arranged in a vertical direction so as to be adjacent to each other, with an interlayer insulation film being interposed on a semiconductor substrate. The resistive change element includes a lower electrode, a resistive change element film made of a metal oxide and an upper electrode. Since the upper electrode on the resistive change element film is formed as part of a plug for the second wiring, a structure in which a side surface of the upper electrode is not in direct contact with the side surface of the metal oxide or the lower electrode is provided so that it is possible to realize excellent device characteristics, even when a byproduct is adhered to the side wall of the metal oxide or the lower electrode in the etching thereof.

摘要翻译： 公开了一种半导体器件，其包括在第一布线和第二布线之间的电阻变化元件，它们在垂直方向上彼此相邻地布置，层间绝缘膜插入在半导体衬底上。 电阻变化元件包括下电极，由金属氧化物和上电极制成的电阻变化元件膜。 由于电阻变化元件膜上的上电极被形成为用于第二布线的插头的一部分，所以上电极的侧表面不与金属氧化物或下电极的侧表面直接接触的结构 即使在其蚀刻中副产物附着在金属氧化物或下电极的侧壁上时，也可以实现优异的器件特性。

公开(公告)号：US20120286231A1

公开(公告)日：2012-11-15

申请号：US13574405

申请日：2011-01-21

申请人： Yukishige Saito ,  Kimihiko Ito ,  Hiromitsu Hada

发明人： Yukishige Saito ,  Kimihiko Ito ,  Hiromitsu Hada

IPC分类号： H01L45/00 ,  H01L21/02

CPC分类号： H01L23/5228 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a semiconductor device including a resistive change element between a first wiring and a second wiring, which are arranged in a vertical direction so as to be adjacent to each other, with an interlayer insulation film being interposed on a semiconductor substrate. The resistive change element includes a lower electrode, a resistive change element film made of a metal oxide and an upper electrode. Since the upper electrode on the resistive change element film is formed as part of a plug for the second wiring, a structure in which a side surface of the upper electrode is not in direct contact with the side surface of the metal oxide or the lower electrode is provided so that it is possible to realize excellent device characteristics, even when a byproduct is adhered to the side wall of the metal oxide or the lower electrode in the etching thereof.

摘要翻译： 公开了一种半导体器件，其包括在第一布线和第二布线之间的电阻变化元件，它们在垂直方向上彼此相邻地布置，层间绝缘膜插入在半导体衬底上。 电阻变化元件包括下电极，由金属氧化物和上电极制成的电阻变化元件膜。 由于电阻变化元件膜上的上电极被形成为用于第二布线的插头的一部分，所以上电极的侧表面不与金属氧化物或下电极的侧表面直接接触的结构 即使在其蚀刻中副产物附着在金属氧化物或下电极的侧壁上时，也可以实现优异的器件特性。

公开(公告)号：US20120267598A1

公开(公告)日：2012-10-25

申请号：US13499956

申请日：2010-10-04

申请人： Yukihiro Sakotsubo ,  Masayuki Terai ,  Munehiro Tada ,  Yuko Yabe ,  Yukishige Saito

发明人： Yukihiro Sakotsubo ,  Masayuki Terai ,  Munehiro Tada ,  Yuko Yabe ,  Yukishige Saito

IPC分类号： H01L47/00 ,  H01L21/02

CPC分类号： H01L21/02186 ,  H01L21/02183 ,  H01L21/022 ,  H01L21/02244 ,  H01L21/02266 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608

摘要： A semiconductor device includes at least first and second electrodes, and a layer including a transition metal oxide layer sandwiched between the first and second electrodes. The transition metal oxide layer includes first and second transition metal oxide layers formed of different first and second transition metals, respectively. The first transition metal oxide layer is provided on the first electrode side, the second transition metal oxide layer is provided on the second electrode side, the first transition metal oxide layer and the second transition metal oxide layer are in contact with each other, the first transition metal oxide layer has an oxygen concentration gradient from the interface between the first transition metal oxide layer and the second transition metal oxide layer toward the first electrode side, and the oxygen concentration at the interface is greater than the oxygen concentration on the first electrode side.

摘要翻译： 半导体器件至少包括第一和第二电极，以及包括夹在第一和第二电极之间的过渡金属氧化物层的层。 过渡金属氧化物层分别包括由不同的第一和第二过渡金属形成的第一和第二过渡金属氧化物层。 第一过渡金属氧化物层设置在第一电极侧，第二过渡金属氧化物层设置在第二电极侧，第一过渡金属氧化物层和第二过渡金属氧化物层彼此接触，第一过渡金属氧化物层 过渡金属氧化物层具有从第一过渡金属氧化物层和第二过渡金属氧化物层之间的界面朝向第一电极侧的氧浓度梯度，并且界面处的氧浓度大于第一电极侧的氧浓度 。

公开(公告)号：US06933569B2

公开(公告)日：2005-08-23

申请号：US10668349

申请日：2003-09-24

申请人： Risho Koh ,  Shigeharu Yamagami ,  Jong-wook Lee ,  Hitoshi Wakabayashi ,  Yukishige Saito ,  Atsushi Ogura ,  Mitsuru Narihiro ,  Kohichi Arai ,  Hisashi Takemura ,  Tohru Mogami ,  Toyoji Yamamoto ,  Yukinori Ochiai

发明人： Risho Koh ,  Shigeharu Yamagami ,  Jong-wook Lee ,  Hitoshi Wakabayashi ,  Yukishige Saito ,  Atsushi Ogura ,  Mitsuru Narihiro ,  Kohichi Arai ,  Hisashi Takemura ,  Tohru Mogami ,  Toyoji Yamamoto ,  Yukinori Ochiai

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L21/01

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78615 ,  H01L29/78621

摘要： A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.

摘要翻译： 半导体器件包括形成在绝缘体上的半导体层，形成在半导体层上的栅极绝缘膜，形成在栅极绝缘膜上并沿第一方向延伸的栅电极，在两侧的半导体层中形成的源/漏区 所述半导体层中的主体接触区域，其中比所述栅极绝缘膜更厚的场绝缘膜介于所述半导体层和所述栅电极的延伸部分之间的部分隔离区域，以及完全隔离区域 去除绝缘体上的半导体层。 完全隔离区域形成为与平行于源极/漏极区域的第一方向的一侧的至少一部分接触。