公开(公告)号：US11057223B2

公开(公告)日：2021-07-06

申请号：US16157098

申请日：2018-10-11

申请人： eMemory Technology Inc.

发明人： Meng-Yi Wu ,  Hsin-Ming Chen

IPC分类号： H04L29/00 ,  H04L9/32 ,  H04L9/08 ,  H04L9/30 ,  H04L29/06 ,  G11C11/56 ,  G11C16/04 ,  H01L27/11524 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H02H9/04

摘要： The communication system includes a communication buffer and a communication terminal. The communication buffer includes a physical unclonable function (PUF) device, and the communication buffer provides a security key generated by the PUF device. The communication terminal is coupled to the communication buffer, and transmits a mapping request to the communication buffer to ask for the security key. The communication terminal manipulates the transmission data with the security key to generate the encrypted data, and transmits the encrypted data to the communication buffer. The communication buffer further restores the transmission data from the encrypted data according to the security key.

公开(公告)号：US11050575B2

公开(公告)日：2021-06-29

申请号：US16223184

申请日：2018-12-18

申请人： eMemory Technology Inc.

发明人： Meng-Yi Wu ,  Chih-Min Wang ,  Hsin-Ming Chen

IPC分类号： H04L9/32 ,  H04L9/06 ,  H04L9/08

摘要： An entanglement and recall system includes an antifuse-type PUF cell array and a processing circuit. The antifuse-type PUF cell array generates at least one key. The processing circuit is connected with the antifuse-type PUF cell array to receive the at least one key. While an entanglement action is performed, the processing circuit receives a plain text and the at least one key and generates a cipher text according to the plain text and the at least one key. While a recall action is performed, the processing circuit receives the cipher text and the at least one key and generates the plain text according to the cipher text and the at least one key.

公开(公告)号：US20180102909A1

公开(公告)日：2018-04-12

申请号：US15726470

申请日：2017-10-06

申请人： eMemory Technology Inc.

发明人： Meng-Yi Wu ,  Hsin-Ming Chen

IPC分类号： H04L9/32 ,  G11C17/16 ,  G11C17/18

CPC分类号： H04L9/3278 ,  G11C17/16 ,  G11C17/18

摘要： An antifuse physically unclonable function (PUF) unit includes a first sub-antifuse cell, a second sub-antifuse cell, a connection circuit, a first copying circuit and a first reading circuit. The first sub-antifuse cell includes a first antifuse transistor. The second sub-antifuse cell includes a second antifuse transistor. The connection circuit is connected between a source/drain terminal of the first antifuse transistor and a source/drain terminal of the second antifuse transistor. The first copying circuit is connected with the first sub-antifuse cell, and includes a third antifuse transistor. The first reading circuit is connected with the first copying circuit. Moreover, the first reading circuit generates a random code according to a state of the third antifuse transistor.

公开(公告)号：US20170345828A1

公开(公告)日：2017-11-30

申请号：US15604672

申请日：2017-05-25

申请人： eMemory Technology Inc.

发明人： Meng-Yi Wu ,  Hsin-Ming Chen

IPC分类号： H01L27/112 ,  H01L29/423 ,  H01L29/165 ,  H01L29/16 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L23/525 ,  G11C17/18 ,  H01L29/78 ,  G11C17/16

CPC分类号： H02M3/07 ,  G11C5/145 ,  G11C5/147 ,  G11C7/06 ,  G11C7/062 ,  G11C7/065 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C11/419 ,  G11C17/165 ,  G11C17/18 ,  G11C2207/002 ,  H01L23/5252 ,  H01L27/11206 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/7848 ,  H01L29/7851 ,  H02M2003/075 ,  H03K3/012 ,  H03K5/134 ,  H03K5/159 ,  H03K17/687 ,  H03K2005/00195

摘要： A non-volatile memory (NVM) includes a fin structure, a first fin field effect transistor (FinFET), a second FinFET, an antifuse structure, a third FinFET, and a fourth FinFET. The antifuse structure is formed on the fin structure and has a sharing gate, a single diffusion break (SDB) isolation structure, a first source/drain region, and a second source/drain region. The SDB isolation structure isolates the first source/drain region and the second source/drain region. The first FinFET, the second FinFET and the first antifuse element compose a first one time programmable (OTP) memory cell, and the third FinFET, the fourth FinFET and the second antifuse element compose a second OTP memory cell. The first OTP memory cell and the second OTP memory cell share the antifuse structure.

公开(公告)号：US09613714B1

公开(公告)日：2017-04-04

申请号：US15209079

申请日：2016-07-13

申请人： eMemory Technology Inc.

发明人： Wei-Zhe Wong ,  Hsin-Ming Chen ,  Meng-Yi Wu

IPC分类号： G11C17/00 ,  G11C17/16 ,  G11C17/18 ,  G06F12/14 ,  H04L9/32 ,  G11C29/00 ,  G11C16/22 ,  G11C7/24 ,  G11C5/06

CPC分类号： G11C17/18 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/1076 ,  G06F12/1408 ,  G06F21/72 ,  G06F21/73 ,  G06F2212/1052 ,  G06F2212/402 ,  G11C5/063 ,  G11C7/10 ,  G11C7/22 ,  G11C7/24 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/22 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C17/16 ,  G11C29/785 ,  H01L27/11206 ,  H03K3/356113 ,  H04L9/3278

摘要： A one time programming memory cell includes a selecting circuit, a first antifuse storing circuit and a second antifuse storing circuit. The selecting circuit is connected with a bit line and a word line. The first antifuse storing circuit is connected between a first antifuse control line and the selecting circuit. The second antifuse storing circuit is connected between a second antifuse control line and the selecting circuit.

公开(公告)号：US09281074B2

公开(公告)日：2016-03-08

申请号：US14222684

申请日：2014-03-24

申请人： eMemory Technology Inc.

发明人： Meng-Yi Wu ,  Chih-Hao Huang ,  Hsin-Ming Chen

IPC分类号： G11C17/16 ,  H01L27/10 ,  H01L27/112 ,  G11C17/18 ,  H01L29/78 ,  H01L23/525

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/101 ,  H01L27/11206 ,  H01L27/11286 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a one time programmable (OTP) memory cell including a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal. The following gate transistor has a second gate terminal, a second drain terminal, a second source terminal coupled to the first drain terminal, and two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. The antifuse varactor has a third gate terminal, a third drain terminal, a third source terminal coupled to the second drain terminal, and a third source/drain extension area coupled with the third drain terminal and the third source terminal for shorting the third drain terminal and the third source terminal.

公开(公告)号：US20140340955A1

公开(公告)日：2014-11-20

申请号：US14222684

申请日：2014-03-24

申请人： eMemory Technology Inc.

发明人： Meng-Yi Wu ,  Chih-Hao Huang ,  Hsin-Ming Chen

IPC分类号： G11C17/08

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/101 ,  H01L27/11206 ,  H01L27/11286 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a one time programmable (OTP) memory cell including a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal. The following gate transistor has a second gate terminal, a second drain terminal, a second source terminal coupled to the first drain terminal, and two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. The antifuse varactor has a third gate terminal, a third drain terminal, a third source terminal coupled to the second drain terminal, and a third source/drain extension area coupled with the third drain terminal and the third source terminal for shorting the third drain terminal and the third source terminal.

摘要翻译： 本发明提供一种包括选择栅极晶体管，随后的栅极晶体管和反熔丝变容二极管的一次性可编程（OTP）存储单元。 选择栅极晶体管具有分别耦合到第一漏极端子和第一源极端子的第一栅极端子，第一漏极端子，第一源极端子和两个第一源极/漏极扩展区域。 以下栅极晶体管具有分别耦合到第二漏极端子和第二源极端子的两个第二源极/漏极延伸区域的第二栅极端子，第二漏极端子，耦合到第一漏极端子的第二源极端子。 反熔丝变容二极管具有第三栅极端子，第三漏极端子，耦合到第二漏极端子的第三源极端子和与第三漏极端子和第三源极端子耦合的第三源极/漏极扩展区域，用于短路第三漏极端子 和第三源终端。

公开(公告)号：US20140098591A1

公开(公告)日：2014-04-10

申请号：US14101367

申请日：2013-12-10

申请人： eMemory Technology Inc.

发明人： Chin-Yi Chen ,  Lun-Chun Chen ,  Yueh-Chia Wen ,  Meng-Yi Wu ,  Hsin-Ming Chen

IPC分类号： G11C17/16

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is an OTP memory cell including a first antifuse unit, a second antifuse unit, a select transistor, and a well region. The first and the second antifuse unit respectively include an antifuse layer and an antifuse gate disposed on a substrate in sequence. The select transistor includes a select gate, a gate dielectric layer, a first doped region, and a second doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The first and the second doped region are respectively disposed in the substrate at two sides of the select gate, wherein the second doped region is disposed in the substrate at the periphery of the first and the second antifuse unit. The well region is disposed in the substrate below the first and the second antifuse unit and is connected to the second doped region.

摘要翻译： 提供了包括第一反熔丝单元，第二反熔丝单元，选择晶体管和阱区的OTP存储单元。 第一和第二反熔丝单元分别包括依次设置在基板上的反熔丝层和反熔丝。 选择晶体管包括选择栅极，栅极电介质层，第一掺杂区域和第二掺杂区域。 选择栅极设置在基板上。 栅介质层设置在选择栅极和衬底之间。 第一掺杂区域和第二掺杂区域分别设置在选择栅极两侧的衬底中，其中第二掺杂区域设置在第一和第二反熔丝单元的周边处的衬底中。 阱区设置在第一和第二反熔丝单元下方的衬底中，并连接到第二掺杂区。

公开(公告)号：US10691414B2

公开(公告)日：2020-06-23

申请号：US16111688

申请日：2018-08-24

申请人： eMemory Technology Inc.

发明人： Meng-Yi Wu ,  Hsin-Ming Chen

IPC分类号： G06F7/58 ,  G11C7/06 ,  G09C1/00 ,  H03K3/84 ,  G11C17/18 ,  H01L27/112 ,  H04L9/32 ,  G11C17/16 ,  G06F21/86 ,  H04L9/08 ,  H03K19/21

摘要： A random code generator is installed in a semiconductor chip and includes a PUF cell array, a control circuit and a verification circuit. The PUF cell array includes m×n PUF cells. The control circuit is connected with the PUF cell array. While a enroll action is performed, the control circuit enrolls the PUF cell array. The verification circuit is connected with the PUF cell array. While a verification action is performed, the verification circuit determines that p PUF cells of the PUF cell array are normal PUF cells and generates a corresponding a mapping information, wherein p is smaller than m×n. While the semiconductor chip is enabled, the control circuit reads states of the p normal PUF cells of the PUF cell array according to the mapping information and generates a random code according to the states.

公开(公告)号：US10177924B1

公开(公告)日：2019-01-08

申请号：US16038143

申请日：2018-07-17

申请人： eMemory Technology Inc.

发明人： Hsin-Ming Chen ,  Meng-Yi Wu ,  Po-Hao Huang

IPC分类号： H03K19/00 ,  H04L9/32 ,  G11C7/06 ,  G11C17/16

摘要： A physically unclonable function unit includes and anti-fuse transistor and a control circuit. The anti-fuse transistor has a first terminal, a second terminal, and a gate terminal. The control circuit is coupled to the anti-fuse transistor. During an enroll operation, the control circuit applies an enroll voltage to the gate terminal of the anti-fuse transistor and applies a reference voltage to the first terminal and the second terminal of the anti-fuse transistor. The enroll voltage is higher than the reference voltage, and is high enough to create a rupture path on the gate terminal to the first terminal or to the second terminal.