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    MIS contact structure with metal oxide conductor
    1.
    发明授权
    MIS contact structure with metal oxide conductor 有权

    公开(公告)号：US10147798B2

    公开(公告)日：2018-12-04

    申请号：US15451164

    申请日：2017-03-06

    Applicant: Acorn Technologies, Inc.

    Inventor： Paul A. Clifton ,  Andreas Goebel

    IPC: H01L29/49 ,  H01L29/36 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L29/08

    Abstract: An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10−5-10−7 Ω-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×1019 cm−3 and less than approximately 10−8 Ω-cm2 when the doping in the semiconductor adjacent the MIS contact is greater than approximately 1020 cm−3.

    Non-linear time domain channel estimation in OFDM systems
    6.
    发明授权
    Non-linear time domain channel estimation in OFDM systems 有权
    OFDM系统中的非线性时域信道估计

    公开(公告)号：US09154337B2

    公开(公告)日：2015-10-06

    申请号：US13841348

    申请日：2013-03-15

    Applicant: Steven C Thompson ,  Roee Kalinksy ,  Fernando Lopez de Victoria

    Inventor： Steven C Thompson ,  Roee Kalinksy ,  Fernando Lopez de Victoria

    IPC: H04L27/01 ,  H04L25/02 ,  H04L27/26 ,  H04L25/03

    CPC classification number: H04L25/0204 ,  H04L25/0212 ,  H04L25/0216 ,  H04L25/022 ,  H04L25/0224 ,  H04L25/03159 ,  H04L27/2647

    Abstract: An OFDM receiver generates an initial channel impulse response in response to a received OFDM signal. The receiver determines the time span within the initial channel impulse response in which significant paths are present. An intermediate channel impulse response estimator identifies paths within the initial channel impulse response and generates an improved intermediate channel impulse response. A channel impulse response estimator performs a second non-linear process to generate a channel impulse response. An equalizer responds to the channel impulse response and the OFDM symbol to equalize the OFDM symbol. Metrics are generated that can be used for effectively stopping the second iterative non-linear process.

    Abstract translation: OFDM接收机响应于接收的OFDM信号产生初始信道脉冲响应。 接收机确定在其中存在有重要路径的初始信道脉冲响应中的时间间隔。 中间信道脉冲响应估计器识别初始信道脉冲响应内的路径，并产生改进的中间信道脉冲响应。 信道脉冲响应估计器执行第二非线性处理以产生信道脉冲响应。 均衡器响应于信道脉冲响应和OFDM符号以均衡OFDM符号。 生成可用于有效停止第二迭代非线性过程的度量。

    BIAXIAL STRAINED FIELD EFFECT TRANSISTOR DEVICES
    8.
    发明申请
    BIAXIAL STRAINED FIELD EFFECT TRANSISTOR DEVICES 审中-公开
    双相应变场效应晶体管器件

    公开(公告)号：US20140170826A1

    公开(公告)日：2014-06-19

    申请号：US13719728

    申请日：2012-12-19

    Applicant: Paul A. Clifton

    Inventor： Paul A. Clifton

    IPC: H01L29/66

    CPC classification number: H01L29/41766 ,  H01L21/28518 ,  H01L21/743 ,  H01L21/76897 ,  H01L29/1054 ,  H01L29/66651 ,  H01L29/7847 ,  H01L29/7849

    Abstract: A process for forming contacts to a field effect transistor provides edge relaxation of a buried stressor layer, inducing strain in an initially relaxed surface semiconductor layer above the buried stressor layer. A process can start with a silicon or silicon-on-insulator substrate with a buried silicon germanium layer having an appropriate thickness and germanium concentration. Other stressor materials can be used. Trenches are etched through a pre-metal dielectric to the contacts of the FET. Etching extends further into the substrate, through the surface silicon layer, through the silicon germanium layer and into the substrate below the silicon germanium layer. The further etch is performed to a depth to allow for sufficient edge relaxation to induce a desired level of longitudinal strain to the surface layer of the FET. Subsequent processing forms contacts extending through the pre-metal dielectric and at least partially into the trenches within the substrate.

    Abstract translation: 用于与场效应晶体管形成接触的工艺提供了埋置的应力层的边缘松弛，从而在掩埋应力层上方的最初松弛的表面半导体层中引起应变。 一种工艺可以从具有适当厚度和锗浓度的掩埋硅锗层的硅或绝缘体上硅衬底开始。 可以使用其他应力源材料。 沟槽通过预金属电介质蚀刻到FET的触点。 蚀刻进一步延伸到衬底中，穿过表面硅层，穿过硅锗层并进入硅锗层下面的衬底。 执行进一步蚀刻到一定深度以允许足够的边缘弛豫以引起对FET的表面层的期望水平的纵向应变。 随后的处理形成延伸穿过预金属电介质并且至少部分地延伸到衬底内的沟槽中的触点。

    Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer
    9.
    发明授权
    Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer 有权
    应变半导体使用应力源的弹性边缘松弛与埋层绝缘层相结合

    公开(公告)号：US08395213B2

    公开(公告)日：2013-03-12

    申请号：US12869978

    申请日：2010-08-27

    Applicant: Paul A. Clifton ,  R. Stockton Gaines

    Inventor： Paul A. Clifton ,  R. Stockton Gaines

    IPC: H01L31/0392 ,  H01L21/20 ,  H01L21/308

    CPC classification number: H01L29/78603 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7846 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/78687

    Abstract: An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

    Abstract translation: SOI晶片包含压应力埋层绝缘体结构。 在一个示例中，应力埋层绝缘体（BOX）可以通过形成氧化硅，氮化硅和氧化硅层而形成在主晶片上，使得氮化硅层受到压应力。 晶片接合在应力绝缘体层上提供表面硅层。 本发明的优选实施方案通过将隔离沟槽蚀刻到具有应力BOX结构的优选SOI衬底中来形成MOS晶体管，以在SOI衬底的表面上限定晶体管有源区。 最优选地，沟槽形成得足够深以穿过受压的BOX结构并且进入到衬底的下面的硅部分的一些距离。 覆盖的硅有源区域将由于弹性边缘松弛而产生拉伸应力。

    Insulated gate field effect transistor having passivated schottky barriers to the channel
    10.
    发明授权
    Insulated gate field effect transistor having passivated schottky barriers to the channel 有权
    绝缘栅场效应晶体管具有通道的钝化肖特基势垒

    公开(公告)号：US08377767B2

    公开(公告)日：2013-02-19

    申请号：US13022559

    申请日：2011-02-07

    Applicant: Daniel E. Grupp ,  Daniel J. Connelly

    Inventor： Daniel E. Grupp ,  Daniel J. Connelly

    IPC: H01L21/338

    CPC classification number: H01L29/47 ,  H01L21/28537 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/0895 ,  H01L29/456 ,  H01L29/4908 ,  H01L29/66143 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/66666 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66848 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/812 ,  H01L29/8126 ,  Y10S438/958

    Abstract: A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω-μm2. The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface. Also, the interface layer may include a separation layer of a material different than the passivating material. Where used, the separation layer has a thickness sufficient to reduce effects of metal-induced gap states in the semiconductor channel.

    Abstract translation: 晶体管包括设置在栅极附近并且在源极和漏极之间的电气路径中的半导体沟道，其中所述沟道和源极或漏极中的至少一个由界面层分开以形成沟道界面层 源极/漏极结，其中半导体通道的费米能级在接合点附近的区域中被取代，并且该结具有小于约1000Ω的比接触电阻。 界面层可以包括通道的半导体的钝化材料，例如氮化物，氟化物，氧化物，氧氮化物，氢化物和/或砷化物。 在一些情况下，界面层基本上由被配置为消除通道的半导体的费米能级的单层或者足以终止半导体通道的全部或足够数量的悬挂键以达到化学稳定性的钝化材料的量 的表面。 此外，界面层可以包括与钝化材料不同的材料的分离层。 在使用时，分离层具有足以减少半导体通道中金属诱发的间隙状态的影响的厚度。

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