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    MEMORY DEVICE WITH COMPOSITE SPACER
    2.
    发明申请
    MEMORY DEVICE WITH COMPOSITE SPACER 有权

    公开(公告)号：US20250169384A1

    公开(公告)日：2025-05-22

    申请号：US19030512

    申请日：2025-01-17

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Fu-Ting SUNG ,  Chern-Yow HSU ,  Shih-Chang LIU

    IPC: H10N70/20 ,  H10N50/01 ,  H10N70/00

    Abstract: A memory device includes a metal structure, a bottom electrode, a storage element, a top electrode, a first spacer, and a second spacer. The metal structure is embedded in a dielectric layer. The bottom electrode is disposed over the metal structure. The top electrode is disposed over the storage element. The first spacer interfaces a first sidewall of the top electrode. The first spacer has a topmost point lower than a topmost point of the top electrode in a cross-sectional view. The second spacer interfaces a second sidewall of the top electrode. The second spacer has a topmost point higher than the topmost point of the top electrode in the cross-sectional view.

    INTEGRATED CIRCUIT PACKAGE AND METHOD
    4.
    发明申请
    INTEGRATED CIRCUIT PACKAGE AND METHOD 有权

    公开(公告)号：US20250167161A1

    公开(公告)日：2025-05-22

    申请号：US18585854

    申请日：2024-02-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Jin Hu ,  Hua-Wei Tseng ,  Wei-Cheng Wu ,  Yung-Ping Chiang ,  An-Jhih Su ,  Der-Chyang Yeh

    IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

    Abstract: A package includes a first die over and bonded to a first side of a package component, where a first bond between the first die and the package component includes a dielectric-to-dielectric bond between a first bonding layer of the first die and a second bonding layer on the package component, and second bonds between the first die and the package component include metal-to-metal bonds between first bonding pads of the first die and second bonding pads on the package component, a first portion of a redistribution structure adjacent to the first die and over the second bonding layer, and a second die over and coupled to the first portion of the redistribution structure using first conductive connectors, where the first conductive connectors are electrically connected to first conductive pads in the second bonding layer.

    INTEGRATED CIRCUIT STRUCTURE
    7.
    发明申请
    INTEGRATED CIRCUIT STRUCTURE 有权

    公开(公告)号：US20250159975A1

    公开(公告)日：2025-05-15

    申请号：US19024566

    申请日：2025-01-16

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chien-Yuan CHEN ,  Hau-Tai SHIEH

    IPC: H10D84/83 ,  H10D84/01 ,  H10D84/03

    Abstract: An integrated circuit (IC) structure includes a first transistor and a second transistor. The first transistor includes a first active region and a first gate disposed on the first active region, in which the first gate has a first effective gate length along a first direction parallel to a lengthwise direction of the first active region. The second transistor includes a second active region and a second gate disposed on the second active region, and includes a plurality of gate structures arranged along the first direction and separated from each other, in which the second gate has a second effective gate length along the first direction, the second effective gate length is n times the first effective gate length, and n is a positive integer greater than 1.

    SRAM CELL WORD LINE STRUCTURE WITH REDUCED RC EFFECTS
    8.
    发明申请
    SRAM CELL WORD LINE STRUCTURE WITH REDUCED RC EFFECTS 有权

    公开(公告)号：US20250159857A1

    公开(公告)日：2025-05-15

    申请号：US19024672

    申请日：2025-01-16

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Hidehiro FUJIWARA ,  Wei-Min CHAN ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

    IPC: H10B10/00 ,  H01L21/321 ,  H01L21/768 ,  H01L23/528 ,  H10D89/10

    Abstract: A device includes first and second gate electrodes, a word line and a first metal island. The first gate electrode corresponds to transistors of a memory cell. The second gate electrode is separated from the first gate electrode and corresponds to the transistors. The word line is coupled to the memory cell and located between the first and the second gate electrodes. The first metal island is configured to couple a first power supply to the memory cell. A first boundary of the first metal island is located between first and second boundaries of the first gate electrode and is located between first and second boundaries of the word line, and each of the first boundary of the first gate electrode and the first boundary of the word line is located between first and second boundaries of the first metal island.

    IMMERSION COOLING SYSTEM AND METHODS
    9.
    发明申请
    IMMERSION COOLING SYSTEM AND METHODS 有权

    公开(公告)号：US20250159846A1

    公开(公告)日：2025-05-15

    申请号：US18506366

    申请日：2023-11-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Sheng LIN ,  Chung-Chiu WU

    IPC: H05K7/20

    Abstract: A method includes: forming a cooled device by cooling a device in and by a first container of an immersion cooler; performing semiconductor processing by a processing tool in data communication with the cooled device; determining whether the cooled device is in a condition to be removed from the immersion cooler; in response to the cooled device not being in the condition, cooling the device by the immersion cooler; and in response to the cooled device being in the condition, removing the device from the first container, including: positioning a second container over the first container; and with the second container in place covering the first container: opening a lid of the first container; and removing the device from the first container.

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