-
公开(公告)号:US20230377905A1
公开(公告)日:2023-11-23
申请号:US17751234
申请日:2022-05-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chien-Li Kuo , Chien-Chen Li , Kuo-Chio Liu , Kuang-Chun Lee , Wen-Yi Lin
IPC: H01L21/48 , H01L23/48 , H01L23/31 , H01L23/498 , H01L23/538 , H01L23/00
CPC classification number: H01L21/486 , H01L23/481 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/73 , H01L2224/04105 , H01L2224/12105 , H01L2924/15311 , H01L2224/73267
Abstract: In an embodiment, a device includes: an integrated circuit die including a die connector; a first through via adjacent the integrated circuit die; an encapsulant encapsulating the first through via and the integrated circuit die; and a redistribution structure on the encapsulant, the redistribution structure including a redistribution line, the redistribution line physically and electrically coupled to the die connector of the integrated circuit die, the redistribution line electrically isolated from the first through via, the redistribution line crossing over the first through via.
-
公开(公告)号:US20250169384A1
公开(公告)日:2025-05-22
申请号:US19030512
申请日:2025-01-17
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Fu-Ting SUNG , Chern-Yow HSU , Shih-Chang LIU
Abstract: A memory device includes a metal structure, a bottom electrode, a storage element, a top electrode, a first spacer, and a second spacer. The metal structure is embedded in a dielectric layer. The bottom electrode is disposed over the metal structure. The top electrode is disposed over the storage element. The first spacer interfaces a first sidewall of the top electrode. The first spacer has a topmost point lower than a topmost point of the top electrode in a cross-sectional view. The second spacer interfaces a second sidewall of the top electrode. The second spacer has a topmost point higher than the topmost point of the top electrode in the cross-sectional view.
-
公开(公告)号:US20250169150A1
公开(公告)日:2025-05-22
申请号:US19027939
申请日:2025-01-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chih Ping Wang , Chao-Cheng Chen , Jr-Jung Lin , Chi-Wei Yang
IPC: H10D64/27 , H01L21/3213 , H10D30/01 , H10D30/62
Abstract: Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.
-
公开(公告)号:US20250167161A1
公开(公告)日:2025-05-22
申请号:US18585854
申请日:2024-02-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yu-Jin Hu , Hua-Wei Tseng , Wei-Cheng Wu , Yung-Ping Chiang , An-Jhih Su , Der-Chyang Yeh
IPC: H01L23/00 , H01L23/498 , H01L25/065 , H01L25/18
Abstract: A package includes a first die over and bonded to a first side of a package component, where a first bond between the first die and the package component includes a dielectric-to-dielectric bond between a first bonding layer of the first die and a second bonding layer on the package component, and second bonds between the first die and the package component include metal-to-metal bonds between first bonding pads of the first die and second bonding pads on the package component, a first portion of a redistribution structure adjacent to the first die and over the second bonding layer, and a second die over and coupled to the first portion of the redistribution structure using first conductive connectors, where the first conductive connectors are electrically connected to first conductive pads in the second bonding layer.
-
公开(公告)号:US20250167037A1
公开(公告)日:2025-05-22
申请号:US18512146
申请日:2023-11-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chia-Hsi Wang , Yen-Yu Chen , Yi-Hu Lo , Pei-Shih Tsai , Zong-Kun Lin
IPC: H01L21/687 , H01L21/306 , H01L21/67
Abstract: A wafer chuck assembly is provided. In one embodiment, the chuck assembly comprises a hub, a plurality of arms mounted to the hub and a plurality of holders. Each arm extends outwardly from the hub, and each arm has a proximal end adjacent the hub and a distal end remote from the hub. Each holder is mounted at the distal end of each respective arm, and each holder has a plurality of support pins configured to support a wafer.
-
公开(公告)号:US20250167002A1
公开(公告)日:2025-05-22
申请号:US19027220
申请日:2025-01-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chien-Hua Huang , Cherng-Shiaw Tsai , Tzu-Hui Wei
IPC: H01L21/311 , H01L21/02 , H01L21/033 , H01L21/321 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H10D84/01 , H10D84/03
Abstract: An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.
-
公开(公告)号:US20250159975A1
公开(公告)日:2025-05-15
申请号:US19024566
申请日:2025-01-16
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Chien-Yuan CHEN , Hau-Tai SHIEH
Abstract: An integrated circuit (IC) structure includes a first transistor and a second transistor. The first transistor includes a first active region and a first gate disposed on the first active region, in which the first gate has a first effective gate length along a first direction parallel to a lengthwise direction of the first active region. The second transistor includes a second active region and a second gate disposed on the second active region, and includes a plurality of gate structures arranged along the first direction and separated from each other, in which the second gate has a second effective gate length along the first direction, the second effective gate length is n times the first effective gate length, and n is a positive integer greater than 1.
-
公开(公告)号:US20250159857A1
公开(公告)日:2025-05-15
申请号:US19024672
申请日:2025-01-16
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Hidehiro FUJIWARA , Wei-Min CHAN , Chih-Yu LIN , Yen-Huei CHEN , Hung-Jen LIAO
IPC: H10B10/00 , H01L21/321 , H01L21/768 , H01L23/528 , H10D89/10
Abstract: A device includes first and second gate electrodes, a word line and a first metal island. The first gate electrode corresponds to transistors of a memory cell. The second gate electrode is separated from the first gate electrode and corresponds to the transistors. The word line is coupled to the memory cell and located between the first and the second gate electrodes. The first metal island is configured to couple a first power supply to the memory cell. A first boundary of the first metal island is located between first and second boundaries of the first gate electrode and is located between first and second boundaries of the word line, and each of the first boundary of the first gate electrode and the first boundary of the word line is located between first and second boundaries of the first metal island.
-
公开(公告)号:US20250159846A1
公开(公告)日:2025-05-15
申请号:US18506366
申请日:2023-11-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wei-Sheng LIN , Chung-Chiu WU
IPC: H05K7/20
Abstract: A method includes: forming a cooled device by cooling a device in and by a first container of an immersion cooler; performing semiconductor processing by a processing tool in data communication with the cooled device; determining whether the cooled device is in a condition to be removed from the immersion cooler; in response to the cooled device not being in the condition, cooling the device by the immersion cooler; and in response to the cooled device being in the condition, removing the device from the first container, including: positioning a second container over the first container; and with the second container in place covering the first container: opening a lid of the first container; and removing the device from the first container.
-
10.
公开(公告)号:US20250157531A1
公开(公告)日:2025-05-15
申请号:US19022593
申请日:2025-01-15
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Yi-Hsin NIEN , Wei-Chang ZHAO , Chih-Yu LIN , Hidehiro FUJIWARA , Yen-Huei CHEN , Ru-Yu WANG
IPC: G11C11/419 , G11C5/06 , G11C11/412
Abstract: A memory device includes a first word line and a second word line. The first word line is configured to transmit a first word line signal to a first set of memory cells. A first portion of the first word line is formed in a first metal layer, and a second portion of the first word line is formed in a second metal layer above the first metal layer. The second word line is configured to transmit a second word line signal to a second set of memory cells. A first portion of the second word line is formed in the first metal layer. A second portion of the second word line is formed in the second metal layer. The second portion of the first word line is partially overlapped with the second portion of the second word line.
-
-
-
-
-
-
-
-
-