公开(公告)号：US12230615B2

公开(公告)日：2025-02-18

申请号：US17558592

申请日：2021-12-22

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Jiraphat Charoenratpratoom ,  Phongsak Sawasdee ,  Wannasat Panphrom

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

Abstract: An embodiment related to a package is disclosed. The package includes a component mounted to a die attach region on a package substrate. A passive component with first and second passive component terminals is vertically attached to the package substrate. An encapsulant is disposed over the package substrate to encapsulate the package. In one embodiment, an external component is stacked above the encapsulant and is electrically coupled to the encapsulated package.

公开(公告)号：US20240339484A1

公开(公告)日：2024-10-10

申请号：US18747638

申请日：2024-06-19

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： IL Kwon Shim ,  Jeffrey Punzalan

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L27/14685 ,  H01L23/315 ,  H01L24/29 ,  H01L27/14625 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/48225

Abstract: A semiconductor device has a substrate. A semiconductor die with a photosensitive circuit is disposed over the substrate. A lens comprising a protective layer is disposed over the photosensitive circuit. An encapsulant is deposited over the substrate, semiconductor die, and lens. The protective layer is removed after depositing the encapsulant.

公开(公告)号：US12100719B2

公开(公告)日：2024-09-24

申请号：US17352348

申请日：2021-06-20

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Jeffrey Punzalan ,  Il Kwon Shim

IPC: H01L27/146

CPC classification number: H01L27/14618 ,  H01L27/14683

Abstract: A semiconductor package and method for forming thereof are disclosed. The package includes a package substrate having a die region with a die attached thereto. An encapsulant is disposed to cover encapsulation region of the package substrate. A protective cover is disposed over the die and attached to the encapsulant by a cover adhesive. The protective cover is supported by a lower portion of step shaped inner encapsulant sidewalls.

公开(公告)号：US11901308B2

公开(公告)日：2024-02-13

申请号：US17382283

申请日：2021-07-21

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Saravuth Sirinorakul ,  Il Kwon Shim ,  Kok Chuen Lock ,  Roel Adeva Robles ,  Eakkasit Dumsong

IPC: H01L23/552 ,  H01L23/36 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/495

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49503 ,  H01L24/32 ,  H01L2224/32245

Abstract: The present disclosure is directed to improving EMI shielding to provide more reliable semiconductor packages. The semiconductor package may be, for example, a lead frame including one or multiple dies attached thereto. The semiconductor package may include only wire bonds or a combination of clip bonds and wire bonds. An integrated shielding structure may be disposed in between the package substrate and the encapsulant to shield internal and/or external EMI. For example, a top surface of the integrated shield structure is exposed.

公开(公告)号：US11784102B2

公开(公告)日：2023-10-10

申请号：US17389294

申请日：2021-07-29

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Eakkasit Dumsong ,  Mike Jayson Candelario ,  Phongsak Sawasdee ,  Jiraphat Charoenratpratoom ,  Paweena Phatto ,  Maythichai Saithong

IPC: H01L23/053 ,  H01L21/52 ,  H01L23/00

CPC classification number: H01L23/053 ,  H01L21/52 ,  H01L23/564

Abstract: A semiconductor package and method for forming thereof are disclosed. The package includes a package substrate having a die cavity with a die attached therein. The package substrate also includes a cavity for bonding a cap thereto to form a hermetic package. The cap is bonded to the cavity using sealing rings.

公开(公告)号：US20230274979A1

公开(公告)日：2023-08-31

申请号：US18175124

申请日：2023-02-27

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Dzafir Bin Mohd Shariff ,  Enrique E. Sarile, JR. ,  Jackson Fernandez Rosario ,  Ronnie M. De Villa ,  Chan Loong Neo ,  Il Kwon Shim

IPC: H01L21/78 ,  H01L29/06 ,  H01L21/683

CPC classification number: H01L21/78 ,  H01L29/0657 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L21/3065

Abstract: Reliable plasma dicing of a processed wafer with a die attach film (DAF) attached to the bottom wafer surface to singulate it into individual dies is disclosed. Laser processing is employed to form mask openings in a passivation stack of a processed wafer to serve as a dicing mask. Laser processing is employed to form a modified layer with cracks on a bottom portion of the wafer. Plasma dicing partially dices the processed wafer to about the modified layer. The dicing tape is expanded laterally away from the center of the partially diced processed wafer, singulating it into individual dies. Singulation of the partially plasma diced processed wafer is facilitated by the modified layer.

公开(公告)号：US11670549B2

公开(公告)日：2023-06-06

申请号：US17125917

申请日：2020-12-17

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Dzafir Bin Mohd Shariff ,  Enrique Jr Sarile ,  Seung Geun Park

IPC: H01L21/78 ,  H01L23/544 ,  H01L21/768

CPC classification number: H01L21/78 ,  H01L21/76838 ,  H01L23/544

Abstract: A semiconductor package which is free of metal debris from backside metallization (BSM) is disclosed. The semiconductor package is singulated by performing a saw street open process from the frontside of the wafer and then includes a singulation process using a plasma etch from the backside of the wafer with BSM. The singulation process results in metal debris free packages.

公开(公告)号：US20230154796A1

公开(公告)日：2023-05-18

申请号：US18056726

申请日：2022-11-18

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Dzafir Bin Mohd Shariff ,  Enrique E. Sarile, JR. ,  Jackson Fernandez Rosario ,  Ronnie M. De Villa ,  Chan Loong Neo

IPC: H01L21/78 ,  H01L23/31

CPC classification number: H01L21/78 ,  H01L23/3171

Abstract: Reliable plasma dicing of wafers to singulate it into individual dies is disclosed. Laser processing is employed to form mask openings in a passivation stack of a processed wafer. The patterned passivation stack serves as a plasma dicing mask for plasma dicing the wafer. The sidewalls of the mask openings may be flat or vertical sidewalls. In other cases, the sidewalls of the mask openings are slanted or chamfered sidewalls. The plasma dices the wafer using first and second plasma etch steps. The first plasma etch step etches to form scalloped sidewalls on the first portion of the die and the second plasma step etches to form flat or vertical sidewalls on a second portion of the die. The second portion of the die is the lower portion of the substrate or wafer. This prevents backside notching to improve reliability.

公开(公告)号：US20230058682A1

公开(公告)日：2023-02-23

申请号：US17454514

申请日：2021-11-11

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Hua Hong Tan ,  Wing Keung Lam ,  Zong Xiang Cai ,  Wei Ming Xian ,  Yao Hong Wu ,  Tao Hu

IPC: B08B1/00 ,  B08B1/02 ,  B08B5/04

Abstract: A semiconductor manufacturing equipment cleaning system has a multi-station cleaning and inspection system. Within semiconductor manufacturing equipment cleaning system, a tray cleaning station uses a first rotating brush passing over a first surface of a carrier and possibly semiconductor die, and a second rotating brush passing over a second surface of the carrier and semiconductor die opposite the first surface of the carrier and semiconductor die. Debris and contaminants dislodged from the first surface and second surface of the carrier by the first rotating brush and second rotating brush are removed under vacuum suction. A conveyor transports the carrier through the multi-station cleaning and inspection system. The first rotating brush and second rotating brush move in tandem across the first surface and second surface of the carrier. Air pressure is injected across the first rotating brush and second rotating brush to further remove debris and contaminants.

公开(公告)号：US11227818B2

公开(公告)日：2022-01-18

申请号：US16942715

申请日：2020-07-29

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Wing Keung Lam ,  Saravuth Sirinorakul ,  Kok Chuen Lock ,  Roel Adeva Robles

IPC: H01L23/495 ,  H01L23/48 ,  H01L21/00 ,  H01R9/00 ,  H05K7/00 ,  H05K7/18 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L25/16 ,  H01L23/00 ,  H01L23/498

Abstract: An embodiment related to a stacked package is disclosed. The stacked package includes a conductive gang with gang legs electrically coupling a second component stacked over a first die to a package substrate. The first die is mounted over a die attach region of the package substrate and electrically coupled to the package substrate.