公开(公告)号：US10361082B2

公开(公告)日：2019-07-23

申请号：US15997298

申请日：2018-06-04

Applicant: ABB Schweiz AG

Inventor： Holger Bartolf ,  Munaf Rahimo ,  Lars Knoll ,  Andrei Mihaila ,  Renato Minamisawa

IPC: H01L21/266 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/16 ,  H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/20

Abstract: A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) for forming two channel layers applying a first mask and applying a p first dopant, for forming two source regions forming a second mask by applying a further layer on the lateral sides of the first mask and applying an n second dopant, for forming two well layers forming a third mask by removing such part of the second mask between the source regions and applying a p third dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers; wherein the well layers surround the plug in the lateral direction and separate it from the two source regions.

公开(公告)号：US10096538B2

公开(公告)日：2018-10-09

申请号：US15485676

申请日：2017-04-12

Applicant: ABB Schweiz AG

Inventor： Bruno Agostini ,  Daniele Torresin ,  Francesco Agostini ,  Mathieu Habert ,  Munaf Rahimo

IPC: H01L23/427 ,  H01L29/16 ,  H01L29/739 ,  H01L29/78 ,  H05K7/20 ,  F25B25/00 ,  H01L23/473 ,  H01L29/20 ,  H01L29/32 ,  H01L29/22

Abstract: A power device comprises at least one power semiconductor module comprising a wide bandgap semiconductor element; and a cooling system for actively cooling the wide bandgap semiconductor element with a cooling medium, wherein the cooling system comprises a refrigeration device for lowering a temperature of the cooling medium below an ambient temperature of the power device; wherein the cooling system is adapted for lowering the temperature of the cooling medium in such a way that a temperature of the wide bandgap semiconductor element is below 100° C.

公开(公告)号：US10037978B2

公开(公告)日：2018-07-31

申请号：US15495174

申请日：2017-04-24

Applicant: ABB Schweiz AG

Inventor： Munaf Rahimo

IPC: H01L25/07 ,  H01L29/739

CPC classification number: H01L25/071 ,  H01L23/48 ,  H01L25/072 ,  H01L25/117 ,  H01L29/0834 ,  H01L29/1608 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2224/0603 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: A semiconductor module and a stack arrangement of semiconductor modules is proposed. The semiconductor module comprises an insulated gate bipolar transistor, a wide band-gap switch, a base plate, and a press device. The insulated gate bipolar transistor and the wide band-gap switch are connected in parallel and are each mounted with a first planar terminal to a side of the base plate. Further, a second planar terminal of the insulated gate bipolar transistor and a second planar terminal of the wind band-gap switch are connected with an electrically conductive connection element, and the press device is arranged on the second planar terminal of the insulated gate bipolar transistor. Hence, when arranging the semiconductor modules in a stack arrangement, any press force is primarily applied to the insulated gate bipolar transistors of the semiconductor modules.

公开(公告)号：US20180047652A1

公开(公告)日：2018-02-15

申请号：US15677625

申请日：2017-08-15

Applicant: ABB Schweiz AG

Inventor： Charalampos Papadopoulos ,  Munaf Rahimo

IPC: H01L23/31 ,  H01L29/78 ,  H01L21/02 ,  H01L29/40

Abstract: A power semiconductor device is provided comprising a wafer, wherein in a termination region of the device a passivation layer structure is formed at least on a portion of a surface of the wafer and the passivation layer structure comprises in an order from the surface of the wafer in a direction away from the wafer a semi insulating layer, a silicon nitride layer, an undoped silicate glass layer and an organic dielectric layer. The silicon nitride layer has a layer thickness of at least 0.5 μm. The organic dielectric layer its attached to the undoped silicate glass layer and the undoped silicate glass layer is attached to the silicon nitride layer.

公开(公告)号：US09887086B2

公开(公告)日：2018-02-06

申请号：US15616382

申请日：2017-06-07

Applicant: ABB Schweiz AG

Inventor： Renato Minamisawa ,  Munaf Rahimo

IPC: H01L21/20 ,  H01L29/16 ,  H01L21/04 ,  H01L29/872 ,  H01L29/06

CPC classification number: H01L21/0485 ,  H01L21/048 ,  H01L21/0495 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/45 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66212 ,  H01L29/872

Abstract: A method for manufacturing a wide bandgap junction barrier Schottky diode having an anode side and a cathode side is provided, wherein an (n+) doped cathode layer is arranged on the cathode side, at least on p doped anode layer is arranged on the anode side, an (n−) doped drift layer is arranged between the cathode layer and the at least one anode layer, which drift layer extends to the anode side, wherein the following manufacturing steps are performed: a) providing an (n+) doped wide bandgap substrate, b) creating the drift layer on the cathode layer, c) creating the at least one anode layer on the drift layer, d) applying a first metal layer on the anode side on top of the drift layer for forming a Schottky contact, characterized in, that e) creating a second metal layer on top of at least one anode layer, wherein after having created the first and the second metal layer, a metal layer on top of the at least one anode layer has a second thickness and a metal layer on top of the drift layer has a first thickness, wherein the second thickness is smaller than the first thickness, f) then performing a first heating step at a first temperature, by which due the second thickness being smaller than the first thickness an ohmic contact is formed at the interface between the second metal layer and the at least one anode layer, wherein performing the first heating step such that a temperature below the first metal layer is kept below a temperature for forming an ohmic contact.

公开(公告)号：US20170294526A1

公开(公告)日：2017-10-12

申请号：US15630491

申请日：2017-06-22

Applicant: ABB Schweiz AG

Inventor： Liutauras Storasta ,  Chiara Corvasce ,  Manuel Le Gallo ,  Munaf Rahimo ,  Arnost Kopta

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/78 ,  H01L29/40 ,  H01L29/36 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7395 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/0865 ,  H01L29/1004 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/402 ,  H01L29/7396 ,  H01L29/7811 ,  H01L29/7819 ,  H01L29/7823

Abstract: A reverse-conducting MOS device is provided having an active cell region and a termination region. Between a first and second main side. The active cell region comprises a plurality of MOS cells with a base layer of a second conductivity type. On the first main side a bar of the second conductivity type, which has a higher maximum doping concentration than the base layer, is arranged between the active cell region and the termination region, wherein the bar is electrically connected to the first main electrode. On the first main side in the termination region a variable-lateral-doping layer of the second conductivity type is arranged. A protection layer of the second conductivity type is arranged in the variable-lateral-doping layer, which protection layer has a higher maximum doping concentration than the maximum doping concentration of the variable-lateral-doping layer in a region attached to the protection layer.

公开(公告)号：US20170271158A1

公开(公告)日：2017-09-21

申请号：US15616382

申请日：2017-06-07

Applicant: ABB Schweiz AG

Inventor： Renato Minamisawa ,  Munaf Rahimo

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/06 ,  H01L29/872

CPC classification number: H01L21/0485 ,  H01L21/048 ,  H01L21/0495 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/45 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66212 ,  H01L29/872

Abstract: A method for manufacturing a wide bandgap junction harrier Schottky diode (1) having an anode side (10) and a cathode side (15) is provided, wherein an (n±) doped cathode layer (2) is arranged on the cathode side (15), at least one p doped anode layer (3) is arranged on the anode side (10), an (n−) doped drift layer (4) is arranged between the cathode layer (2) and the at least one anode layer (3), which drift layer (4) extends to the anode side (10), wherein the following manufacturing steps are performed: a) providing an (n+) doped wide bandgap substrate(100), b) creating the drift layer (4) on the cathode layer (2), c) creating the at least one anode layer (3) on the drift layer (4), d) applying a first metal layer (5) on the anode side (10) on top of the drift layer (4) for forming a Schottky contact (55), characterized in, that e) creating a second metal layer (6) on top of at least one anode layer (3), wherein after having created the first and the second metal layer (5, 6), a metal layer on top of the at least one anode layer (3) has a second thickness (64) and a metal layer on top of the drift layer (4) has a first thickness (54), wherein the second thickness (64) is smaller than the first thickness (54), 1) then performing a first heating step (63) at a first temperature, by which due the second thickness (64) being smaller than the first thickness (54) an ohmic contact (65) is formed at the interface between the second metal layer (6) and the at least one anode layer (3), wherein performing the first healing step (63) such that a temperature below the first metal layer (5) is kept below a temperature for forming an ohmic contact.

公开(公告)号：US10516022B2

公开(公告)日：2019-12-24

申请号：US15997307

申请日：2018-06-04

Applicant: ABB Schweiz AG

Inventor： Holger Bartolf ,  Munaf Rahimo ,  Lars Knoll ,  Andrei Mihaila ,  Renato Minamisawa

IPC: H01L21/00 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/16 ,  H01L29/739 ,  H01L21/02 ,  H01L21/04 ,  H01L21/265 ,  H01L21/266 ,  H01L21/302 ,  H01L21/308 ,  H01L29/08 ,  H01L29/20

Abstract: A wide bandgap semiconductor device is comprising an (n−) doped drift layer between a first main side and a second main side. On the first main side, n doped source regions are arranged which are laterally surrounded by p doped channel layers having a channel layer depth. P+ doped well layers having a well layer depth, which is at least as large as the channel layer depth is arranged at the bottom of the source regions. A p++ doped plug extends from a depth, which is at least as deep as the source layer depth and less deep than the well layer depth, to a plug depth, which is as least as deep as the well layer depth, and having a higher doping concentration than the well layers, is arranged between the source regions and well layers. On the first main side, an ohmic contact contacts as a first main electrode the source regions, the well layers and the plug.

公开(公告)号：US10468321B2

公开(公告)日：2019-11-05

申请号：US15677625

申请日：2017-08-15

Applicant: ABB Schweiz AG

Inventor： Charalampos Papadopoulos ,  Munaf Rahimo

IPC: H01L23/31 ,  H01L21/02 ,  H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L29/861 ,  H01L29/16

Abstract: A power semiconductor device is provided comprising a wafer, wherein in a termination region of the device a passivation layer structure is formed at least on a portion of a surface of the wafer and the passivation layer structure comprises in an order from the surface of the wafer in a direction away from the wafer a semi-insulating layer, a silicon nitride layer, an undoped silicate glass layer and an organic dielectric layer. The silicon nitride layer has a layer thickness of at least 0.5 μm. The organic dielectric layer its attached to the undoped silicate glass layer and the undoped silicate glass layer is attached to the silicon nitride layer.

公开(公告)号：US10411694B2

公开(公告)日：2019-09-10

申请号：US15217571

申请日：2016-07-22

Applicant: ABB Schweiz AG

Inventor： Pietro Cairoli ,  Lukas Hofstetter ,  Matthias Bator ,  Riccardo Bini ,  Munaf Rahimo

IPC: H03K17/567 ,  H03K17/687 ,  H02H7/00 ,  H03K17/10 ,  H03K17/12 ,  H02H3/02

Abstract: A solid state switch has at least one FET-type device and at least one thyristor-type device coupled in parallel to the at least one FET-type device. The at least one FET-type device is constructed with a first power loss profile based on a rated current of an electrical device; and the at least one thyristor-type device is constructed with a second power loss profile based on a surge current associated with the electrical device.